參數(shù)資料
型號(hào)： VSC8140TW
廠商： VITESSE SEMICONDUCTOR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
中文描述： TRANSCEIVER, PBGA208
封裝： 23 X 23 MM, THERMALLY ENHANCED, TBGA-208
文件頁(yè)數(shù)： 13/34頁(yè)
文件大?。?/td> 528K
代理商： VSC8140TW
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
Page 13
9/6/00
VITESSE
Data Sheet
VSC8140
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
G52251-0, Rev. 4.0
Supplies
The VSC8140 is specified as a PECL device with a single positive 3.3V supply. Should the user desire to
use the device in an ECL environment with a negative 3.3V supply, then V
CC
will be ground and V
EE
will be -
3.3V. If used with V
EE
tied to -3.3V, the TTL control signals are still referenced to V
EE
.
Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is
recommended that the V
CC
power supply be decoupled using a 0.1
μ
F and 0.01
μ
F capacitor placed in parallel
on each V
CC
power supply pin as close to the package as possible. If room permits, a 0.001
μ
F capacitor should
also be placed in parallel with the 0.1
μ
F and 0.01
μ
F capacitors mentioned above. Recommended capacitors are
low-inductance ceramic SMT X7R devices. For the 0.1
μ
F capacitor, a 0603 package should be used. The
0.01
μ
F and 0.001
μ
F capacitors can be either 0603 or 0403 packages.
Extra care needs to be taken when decoupling the analog power supply pins (labeled V
CCANA
). In order to
maintain the optimal jitter and loop bandwidth characteristics of the PLL contained in the VSC8140, the analog
power supply pins should be filtered from the main power supply with a 10
μ
H C-L-C pi filter. If preferred, a
ferrite bead may be used to provide the isolation. The 0.1
μ
F and 0.01
μ
F decoupling capacitors are still required
and must be connected to the supply pins between the device and the C-L-C pi filter (or ferrite bead).
For low frequency decoupling, 47
μ
F tantalum low-inductance SMT caps are sprinkled over the board’s
main +3.3V power supply and placed close to the C-L-C pi filter.
If the device is being used in an ECL environment with a -3.3V supply, then all references to decoupling
V
CC
must be changed to V
EE
, and all references to decoupling 3.3V must be changed to -3.3V.
Figure 17: PLL Power Supply Decoupling Scheme
Note: V
CC
can be tied to V
CCANA
V
EE
V
EEANA
V
CC
V
CCANA
V
CCANA
10
μ
H
0.1
μ
F
0.1
μ
F
0.01
μ
F
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