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參數(shù)資料
| 型號： | VSC8116QP1 |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation |
| 中文描述： | TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, HEAT SPREADER, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 358K |
| 代理商： | VSC8116QP1 |
VITESSE
Data Sheet
VSC8116
ATM/SONET/SDH 622/155Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Page 8
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
G52220-0, Rev 4.1
1/8/00
Table 3: Clock Multiplier Unit Performance
(1)
These Reference Clock Jitter limits are required for the outputs to meet SONET system level jitter requirements
(< 10 mUIrms)
Needed to meet SONET output frequency stability requirements
Measured
(2)
(3)
Note: Jitter specification is defined utilizing a 12KHz - 5MHz LP-HP single pole filter.
AC Timing Characteristics
Figure 7: Receive High Speed Data Input Timing Diagram
Table 4: Receive High Speed Data Input Timing Table (
STS-12 Operation
)
Name
Description
Min
Typ
Max
Units
RCd
RCj
RCj
RC
f
OCj
OCj
Reference clock duty cycle
Reference clock jitter (RMS) @ 77.76 MHz ref
(1)
Reference clock jitter (RMS) @ 19.44 MHz ref
(1)
Reference clock frequency tolerance
(2)
Output clock jitter (RMS) @ 77.76 MHz ref
(3)
Output clock jitter (RMS) @ 19.44 MHz ref
(3)
Output frequency
Output clock duty cycle
40
60
13
5
+20
8
15
624
60
%
ps
ps
ppm
ps
ps
MHz
%
-20
OCfrange
OCd
620
40
Parameter
Description
Min
Typ
Max
Units
T
RXCLK
T
RXSU
T
RXH
Receive clock period
Serial data setup time with respect to RXCLKIN
Serial data hold time with respect to RXCLKIN
-
1.608
-
-
-
-
-
ns
ps
ps
250
250
T
RXCLK
T
RXSU
T
RXH
RXCLKIN+
RXCLKIN-
RXDATAIN+
RXDATAIN-
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