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參數(shù)資料
| 型號(hào)： | VSC7212 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | Gigabit Interconnect Chip |
| 中文描述： | 千兆互連芯片 |
| 文件頁數(shù)： | 31/34頁 |
| 文件大小： | 504K |
| 代理商： | VSC7212 |
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VITESSE
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
G52268-0, Rev 3.3
04/10/01
Page 31
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800)-VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
29
FLOCK
I
TTL
F
requency
LOCK
ed Mode. When HIGH indicates that the transmitting
device
’
s REFCLK is frequency-locked to the receiver
’
s word clock.
Controls rate matching (IDLE delete/duplicate) logic along with the WSI
input as defined in Table 6.
B
uilt-
I
n
S
elf
T
est Mode. When HIGH, the transmitter continuously sends a
256 byte incrementing data pattern, and the receiver signals correct
reception of the test pattern with a LOW on TBERR.
EN
coder/
DEC
oder Enable. When HIGH the VSC7212 is configured for 8
bit operation, internal 8B/10B encoding is enabled. When LOW, a 10-bit
interface is used and internal 8B/10B encoding is bypassed.
RESETN
Input. When asserted LOW, the transmitter input skew buffer and
receiver elastic buffer are recentered.
W
ord
S
ync
I
nput. Used to control chip-to-chip alignment and IDLE
character insertion/deletion as defined in Table 6.
W
ord
S
ync
O
utput. Used to set initial chip-to-chip word alignment, and to
maintain alignment by controlling IDLE character insertion/deletion.
JTAG Test Access Port Test Clock Input
JTAG Test Access Port Test Mode Select Input
JTAG Test Access Port Test Data Input
JTAG Test Access Port Test Data Output
JTAG Test Access Port Test Logic Reset Input
27
BIST
I
TTL
28
ENDEC
I
TTL
38
RESETN
I
TTL
39
WSI
I
TTL
45
WSO
O
TTL
79
78
77
74
80
40
41
12
15
TCK
TMS
TDI
TDO
TRSTN
RSVD0
RSVD1
VDDA
VSSA
I
I
I
TTL
TTL
TTL
TTL
TTL
O
I
I
N/A
Reserved Inputs for future use. Set HIGH for compatibility reasons.
P
P
VDD
GND
Analog power supply to PLL.
Analog ground to PLL.
16,24,32
42,84,94
6,11,19,33
44,83,93
49,57,64
70
47,54,59
62,67,72
VDDD
P
VDD
Digital power supply.
VSSD
P
GND
Digital ground.
VDDT
P
VDD
TTL output power supply.
VSST
P
GND
TTL output ground.
3
8
VDDP
VDDR
P
VDD
PECL Output power supply for PTX.
PECL Output power supply for RTX.
If use of an output is not necessary, leave the power supply pin open.
1,25,26
50,51,75
76,100
N/C
Not connected internally.
Pin
Name
I/O
Type
Pin Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VSC7212RG | Gigabit Interconnect Chip |
| VSC7216-01 | Multi-Gigabit Interconnect Chip |
| VSC7216-02 | 740; 38000/740 Series; Microcontroller; Bit Size: 8-bit; ROM: 60K; RAM: 2048; ROM Type: Mask ROM; CPU: 740 core; Minimum Instruction Execution Time (ns): 240 (@16.8MHz); Operating Frequency / Supply Voltage: 1.8 to 5.5V; Operating Ambient Temperature (°C): -20 to 85; Package Code: PLQP0064GA-A (64P6U-A) |
| VSC7217 | Multi-Gigabit Interconnect Chip |
| VSC7226 | 740; 38000/740 Series; Microcontroller; Bit Size: 8-bit; ROM: 60K; RAM: 2048; ROM Type: Mask ROM; CPU: 740 core; Minimum Instruction Execution Time (ns): 240 (@16.8MHz); Operating Frequency / Supply Voltage: 1.8 to 5.5V; Operating Ambient Temperature (°C): -20 to 85; Package Code: PRDP0064BA-A (64P4B) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSC7212RG | 制造商: 功能描述: 制造商:undefined 功能描述: 制造商:VITESSA 功能描述: |
| VSC7214QV11 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fiber-Optic Transceiver |
| VSC7214QV13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fiber-Optic Transceiver |
| VSC7216-01 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Gigabit Interconnect Chip |
| VSC7216-02 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:02 Low Power Quad 1.25Gb/s Backplane Transceiver |
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