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VITESSE
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Page 24
G52268-0, Rev 3.3
04/10/01
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800)-VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 20: REFCLK Timing Waveforms
Table 15: Reference Clock Requirements
Parameters
Description
Min
Max
Units
Conditions
FR
Frequency range
98
49
136
68
MHz
MHz
DUAL = 0
DUAL = 1
| REFCLK (Tx) - REFCLK (Rx) | =
max offset between Tx and Rx device
REFCLKs on one serial link
Measured at 1.4V
FO
Frequency offset
-200
200
ppm
DC
T
H
,T
L
T
RCR
,T
RCF
REFCLK duty cycle
REFLCK and TBC pulse width
REFCLK rise and fall time
REFCLK Jitter Power
3
MHz
∫
35
3
—
65
—
1.5
%
ns
ns
Between V
IL(MAX)
and V
IH(MIN)
REFCLK
Jitter
—
100
ps
RMS for 10
-12
Bit Error Ratio with zero
length external path, tested on a sample
basis
REFCLK
V
IL(MAX)
V
IH(MIN)
T
L
T
H
PhaseNoise
100
Hz