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參數(shù)資料
| 型號： | VSC7177 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Enhanced 2:1 Port Selector for Serial ATA and Serial Attached SCSI |
| 中文描述： | 增強(qiáng)型2:1端口選擇器，用于串行ATA和串行連接SCSI |
| 文件頁數(shù)： | 20/24頁 |
| 文件大小： | 253K |
| 代理商： | VSC7177 |
20 of 24
Revision 4.2
July 29, 2005
Confidential
VSC7177
Data Sheet
Pin Identifications
Table 17. Pin Identifications
Pin Number
Signal
Type
Level
Description
7, 6
15, 14
31, 30
P0OUTP, P0OUTN
P1OUTP, P1OUTN
P2OUTP, P2OUTN
O
High-
Speed
These are the high-speed differential outputs for port 0, port 1,
and port 2. These outputs must be AC-coupled.
3, 4
11, 12
27, 28
P0INP, P0INN
P1INP, P1INN
P2INP, P2INN
I
High-
Speed
These are the high-speed differential inputs for port 0, port 1, and
port 2. These inputs must be AC-coupled.
19
18
PORTSEL0
PORTSEL1
I
LVTTL
These two inputs select the active port (port 0 or port 1) when the
device is in sideband-based port selection mode.
PORTSEL1 is used to choose the port selection mode when the
VSC7177 is operating in protocol-based port selection mode. For
more information on the operating modes, see
Table 1,
page 5
and
“Functional Descriptions”
on page 5.
2
10
26
HIV0
HIV1
HIV2
I
LVTTL
When HIGH, selects the high voltage swing output mode for the
corresponding output buffer and enables pre-emphasis. See
Table 6,
page 11.
24
23
OOBSEL0
OOBSEL1
I
LVTTL
These two inputs control the OOB detector threshold voltage for
all three input ports. See
Table 7,
page 12 for threshold levels.
1
9
P0SLTD
OOBPORT0
O
LVTTL
These status signals can be monitored by the host for diagnostics.
See
Table 2,
page 6 and
Table 5,
page 10.
17
MODE0
I
LVTTL
For sideband-based port selection, MODE0 is used as described
in
Table 3,
page 7. For protocol based port selection, MODE0
must be HIGH.
21
MODE1
I
LVTTL
For sideband-based port selection, MODE1 is used as described
in
Table 3,
page 7. For protocol based port selection, MODE1
must be LOW.
20
VDD
Power
3.3 V power supply for all circuits except the high-speed output
buffers.
8, 16
32
VDD0, VDD1
VDD2
Power
3.3 V output buffer power supply for P0OUTP/N, P1OUTP/N, and
P2OUTP/N, respectively.
25
VDDN
Analog
1.8 V power supply generated by internal voltage regulator.
Connect a 4.7
μ
F capacitor with equivalent series resistance
between 0.5
and 5
to this pin.
5, 13,
22, 29
DAP
VSS
GND
Common ground.
DAP is the exposed die attach pad on the bottom of the device.
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