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參數(shù)資料
| 型號(hào)： | VPX3214C |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Video Pixel Decoders |
| 中文描述： | 視頻解碼器像素 |
| 文件頁數(shù)： | 24/80頁 |
| 文件大?。?/td> | 752K |
| 代理商： | VPX3214C |
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PRELIMINARY DATA SHEET
VPX 3220 A, VPX 3216 B, VPX 3214 C
MICRONAS INTERMETALL
24
Horizontally, the windows are defined by a starting point
and a length. The starting point and the length are both
given relative to the number of pixels in the active portion
of the line (Fig. 3–9).
There are some restrictions in the horizontal window
definition. The total number of active pixels (NPixel)
must be an even number. The maximum value for NPixel
depends on the selected transport clock. For a
20.25 MHz transport clock, the maximum value for
NPixel is 1056. For a 13.5 MHz transport clock, the maxi-
mum value is 800. HLength should also be an even num-
ber. Obviously, the sum of HBegin and HLength may not
be greater than NPixel.
Window boundaries are defined by writing the dimen-
sions into the associated WinDefTab and then setting
the corresponding latch bit in the control word. Window
definition data is latched at the beginning of the next vid-
eo frame. Once the WinDefTab data has been latched,
the latch bit in the control word is reset. By polling the
info-word, the external controller can know when the
window boundary data has been read. Multiple window
definitions within a single frame time are ignored and
can lead to error.
Window
H Begin
64
μ
sec
52.15
μ
sec
H Length
N Pixel
Fig. 3–9:
Horizontal Dimensions of Sampling Window
3.4. Video Data Transfer
The VPX supports two methods of transfer for the
sampled video data: a synchronous mode and an
asynchronous mode. Both modes support all the byte
formats shown in Figs. 2–21 and 2–22, as well as both
alternative transport rates.
In both modes, data arrives at the output FIFO in an
uninterrupted burst with a fixed transport rate. The trans-
port rate is selected by the external controller to be either
13.5 MHz or 20.25 MHz. The duration of the burst is
measured in clock periods of the transport clock and is
equal to the number of pixels per output line.
The control signals on the three pins: PIXCLK, FE/VACT,
and HF/FSY, LLC regulate the data transfer. Their func-
tion is dependent on the transfer mode (sync., or
async.). For the synchronous mode, the signals at these
pins are PIXCLK (internal), VACT, and LLC (respective-
ly). For the asynchronous mode, the signals at these
pins are PIXCLK (external), FE, and HF.
3.4.1. Synchronous Output
In the synchronous transfer mode, data is transferred
synchronous to an internally generated PIXCLK. The
frequency of the PIXCLK is equal to the selected trans-
port rate. In the single clock mode, data can be latched
onto the falling edge of PIXCLK. In double clock mode,
output data must be latched onto both clock edges. The
double clock mode is supported for the 13.5 MHz trans-
port rate only. The available transfer bandwidths at the
ports are therefore 13.5 MHz, 20.25 MHz (single clock),
and 27.0 MHz (double clock).
The video data is output in a continuous stream. The
PIXCLK is free running. The VACT signal flags the pres-
ence of valid output data. Fig. 3–10 illustrates the rela-
tionship between the video port data, VACT, and
PIXCLK. Whenever a line of video data should be sup-
pressed (line dropping, switching between analog in-
puts), it is done by suppression of the VACT signal.
Fig. 3–11 illustrates the temporal relationship between
the VACT and the HREF signals as a function of the
number of pixels per output line and the horizontal di-
mensions of the window. The duration of the active peri-
od of the HREF (Fig. 3–11
,
points B, D) is fixed. Table
3–2 lists the positions of the VACT edges (points A, C)
relative to those of HREF.
The LLC signal is provided as an additional support for
the 13.5 MHz single clock mode. The LLC provides a 2x
PIXCLK signal (27 MHz) for interface to external compo-
nents which rely on the Philips transfer protocols. In the
single clock 13.5 MHz mode, the pixel data can be
latched onto alternate rising edges of the LLC.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VPX3224D | Video Pixel Decoders |
| VPX3224E | Video Pixel Decoders |
| VPX322XE | Video Pixel Decoders |
| VQ1000J | N-Channel Enhancement-Mode MOSFET Transistor(最小漏源擊穿電壓60V,夾斷電流0.225A的N溝道增強(qiáng)型MOSFET晶體管) |
| VQ1000J | N-Channel 60-V (D-S) MOSFET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VPX3214C(PLCC44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3214C(QFP44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3216B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders |
| VPX3216B(PLCC44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
| VPX3216B(QFP44) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit |
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