參數(shù)資料
型號(hào): VPX3214C
廠商: Electronic Theatre Controls, Inc.
英文描述: Video Pixel Decoders
中文描述: 視頻解碼器像素
文件頁(yè)數(shù): 16/80頁(yè)
文件大小: 752K
代理商: VPX3214C
PRELIMINARY DATA SHEET
VPX 3220 A, VPX 3216 B, VPX 3214 C
MICRONAS INTERMETALL
16
2.5. Output Pixel Format
The output formatting stage (Fig. 2–20) receives the vid-
eo samples from the color component stage, performs
the necessary bit packing, buffers the data for transmis-
sion, and channels the output via one or both 8-bit ports.
Data transfer can be either synchronous to an internally
generated pixel clock or asynchronous with FIFO and
status signals.
Format section controls:
– byte formats (bit order)
– number of ports (A only or both A and B)
– clock speed (single or double).
The video samples (and alpha key) arrive from the color
component stage at one of two pixel transport rates:
13.5 MHz or 20.25 MHz. This clock rate is selectable via
I
2
C command. However, the use of the 13.5 MHz clock
assumes that the resizer is reducing the number of ac-
tive samples per line to a maximum of 768 pixels.
2.5.1. Output Ports
The two 8-bit ports produce TTL level signals coded in
binary offset. The ports can be tristated either via the
output enable pin (OE) or via I
2
C commands.
2.5.2. Output Port Formats
The format of output data depends on three parameters:
the selected signal format, the number of active ports,
and the output clock rate. For a given clock rate and
number of active ports, a subset of these output formats
is supported. Figures 2–21 and 2–22 illustrate this de-
pendency. All single port transfers use port A only.
B
O
O
Alpha Key
Port 1
Port 2
OE
Clock
Generation
PIXCLK
FE
HF
Syncr / Asyncr
1
24
24
24
1
1
8
8
Video
Samples
Alpha
Key
8
8
I
2
C reg
Fig. 2–20:
Output formatting stage
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