參數(shù)資料
型號(hào): VPC3200A
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
元件分類: 消費(fèi)家電
英文描述: Comb Filter Video Processor
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝: PLASTIC, QFP-80
文件頁(yè)數(shù): 5/78頁(yè)
文件大?。?/td> 1245K
代理商: VPC3200A
ADVANCE INFORMATION
VPC 323xD, VPC 324xD
Micronas
5
Comb Filter Video Processor
1. Introduction
The VPC 323xD/324xD is a high-quality, single-chip
video front-end, which is targeted for 4:3 and 16:9, 50/
60 and 100/120 Hz TV sets. It can be combined with
other members of the DIGIT3000 IC family (such as
DDP 33x0A/B, TPU 3040) and/or it can be used with
3rd-party products.
The main features of the VPC 323xD/324xD are
– high-performance adaptive 4H comb filter Y/C sepa-
rator with adjustable vertical peaking
– multi-standard color decoder PAL/NTSC/SECAM
including all substandards
– four CVBS, one S-VHS input, one CVBS output
– two RGB/YC
r
C
b
component inputs, one Fast Blank
(FB) input
– integrated high-quality A/D converters and associ-
ated clamp and AGC circuits
– multi-standard sync processing
– linear horizontal scaling (0.25 ... 4), as well as
non-linear horizontal scaling ‘panorama vision’
– PAL+ preprocessing (VPC 323xD)
– line-locked clock, data and sync, or 656-output inter-
face (VPC 323xD)
– display and deflection control (VPC 324xD)
– peaking, contrast, brightness, color saturation and
tint for RGB/YC
r
C
b
and CVBS/S-VHS
– high-quality soft mixer controlled by Fast Blank
– PIP processing for four picture sizes (
normal size) with 8 bit resolution
, or
of
– 15 predefined PIP display configurations and expert
mode (fully programmable)
– control interface for external field memory
– I
2
C-Bus Interface
– one 20.25 MHz crystal, few external components
– 80-pin PQFP package
1.1. System Architecture
Fig.1–1 shows the block diagram of the video proces-
sor
Fig. 1–1:
.Block diagram of the VPC 323xD
1
4
1
16
------
, ,
1
36
---
Mixer
CIN
VIN1
VIN2
VIN3
VIN4
VOUT
Adaptive
Comb
Filter
Color
Decoder
Output
Formatter
Matrix
Contrast
Saturation
Brightness
Tint
2D Scaler
PIP
Panorama
Mode
ITU-R 656
ITU-R 601
Memory
Control
Sync
+
Clock
Generation
AGC
2
×
ADC
NTSC
PAL
NTSC
PAL
SECAM
CrCb
OUT
Y OUT
YCOE
FIFO
CNTL
H Sync
V Sync
AVO
I
2
C Bus
20.25 MHz
RGB/
YCrCb
FB
Y
Cb
Cr
Y
Cb
Cr
Y/G
U/B
Y
Cb
Cr
LL Clock
Saturation
Tint
Analog
Front-end
Contrast
Brightness
Peaking
Clock
Gen.
I
2
C Bus
V/R
FB
FB
RGB/
YCrCb
Analog
Component
Front-End
4 x ADC
Processing
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