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ADVANCE INFORMATION
VPC 323xD, VPC 324xD
Micronas
33
h’23
16
w/r
OUTPUT STRENGTH:
bit[3:0]
0..15
output pin strength
(0 = strong, 15 = weak)
address of output pin
FIFO control pins FFIE, FFOE, FFWR,
FFRE and FFRSTWR
SYNC pins AVO, HS, HC, INTERLACE, VS
read/write output strength
reserved (set to 0)
bit[9:4]
32
33
0/1
bit[10]
bit[15:11]
0
0
0
0
OUTSTR
PADSTR
PADADD
PADWR
h’30
8
w/r
V-SYNC DELAY CONTROL:
bit[7:0]
VS delay (8 LLC clock cycles per LSB)
0
VSDEL
VSDEL
656 Interface
h’24
8
w/r
656 OUTPUT INTERFACE
bit [0]
1
disable hor. & vert. blanking of invalid
data in 656 mode
use vertical window as VFLAG
use vsync as VFLAG
enable suppression of 656-headers
during invalid video lines
enable ITU-656 output format
LLC1/LLC2 used as reference clock
output mode: DIGIT 3000 / LLC
bit [1]
0
1
bit [2]
bit [3]
bit [4]
bit [5]
0/1
0/1
0
0
0
0
0
1
OUT656
DBLNK
VSMODE
HSUP
656enable
DBLCLK
OMODE
Sync Generator
h’21
16
w/r
LINE LENGTH:
bit[10:0]
LINE LENGTH register
In LLC mode, this register defines the
cycle of the sync counter which generates
the SYNC pulses.
In LLC mode, the synccounter counts from
0 to LINE LENGTH, so this register has to
be set to “number of pixels per line –1”.
In DIGIT3000 mode, LINE LENGTH has to
be set to 1295 for correct adjustment of
vertical signals.
reserved (set to 0)
bit[15:11]
1295
LINLEN
h’26
16
w/r
HC START:
bit[10:0]
HC START defines the beginning of the
HC signal in respect to the value of the
sync counter.
reserved (set to 0)
bit[15:11]
50
HCSTRT
h’27
16
w/r
bit[10:0]
HC STOP defines the end of the HC signal
in respect to the value of the sync counter.
reserved (set to 0)
bit[15:11]
800
HCSTOP
I
2
C Sub-
address
Number
of bits
Mode
Function
Default
Name