- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄297772 > VMS115 TELECOM, DATA ENCRYPTION CIRCUIT, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | VMS115 |
| 元件分類： | 加密電路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 22/64頁 |
| 文件大?。?/td> | 572K |
| 代理商： | VMS115 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
VLSI Technology, a subsidiary of Philips Semiconductors
8/10/99
29
Revision: 2.3
906
Data Sheet
Context Write Timing Diagram
5.3.4.5
Context Read
The context data read can be performed at any time without regard to the ORDY signal (see tim-
ing diagram). However, the ORDY signal is used at the end of a packet to signal that the HMAC
digest is ready to be read as part of the context. Therefore, the ORDY signal can be used to queue
a DMA transaction that will read the HMAC digest at the proper time. The context read pointer is
used to determine the value that is read from the context read table. The context read pointer is
incremented after every read of the context read table. A register access will not reset the context
read pointer.
Context Read Timing Diagram
5.3.4.6
Packet Data Write
The packet data is transferred into the VMS115 device with the packet data write command. The
IRDY signal must be high before starting the packet data write command (see timing diagram). If
Note: ‘other’ is any code other than context write (110) or register (X00) and context pointer will reset to zero
Note: context write will flush all state machines and reset ORDY and IRDY
123
4567
8
111
XX
CT0
111
XX
CT1
CT2
CT3
111
XX
CT4
910
other
A
11
12
13
14
15
111
XX
CT0
16
CLK
CE_L
CMD[2:0]
A
DQ
IRDY
ORDY
Note: ‘other’ is any code other than context read (010) or register (X00) and context pointer will reset to zero
12
3
45
6
7
8
011
XX
CT0
011
XX
CT1
CT2
CT3
011
XX
910
other
A
11
12
13
14
15
011
XX
CT4
CT0
16
= Driven by VMS115
CLK
CE_L
CMD[2:0]
A
DQ
IRDY
ORDY
相關PDF資料 |
PDF描述 |
|---|---|
| VN-84-AR-1 | 9800 MHz - 10400 MHz RF/MICROWAVE SGL POLE TRIPLE THROW SWITCH, 1.7 dB INSERTION LOSS |
| VN-84-ARD-1 | 9800 MHz - 10400 MHz RF/MICROWAVE SGL POLE TRIPLE THROW SWITCH, 1.7 dB INSERTION LOSS |
| VN-84-AS-1 | 9800 MHz - 10400 MHz RF/MICROWAVE SGL POLE TRIPLE THROW SWITCH, 1.7 dB INSERTION LOSS |
| VN-86-AR-1 | 10000 MHz - 10500 MHz RF/MICROWAVE SGL POLE TRIPLE THROW SWITCH, 1.7 dB INSERTION LOSS |
| VN-86-ARD-1 | 10000 MHz - 10500 MHz RF/MICROWAVE SGL POLE TRIPLE THROW SWITCH, 1.7 dB INSERTION LOSS |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| VMS1177 | 制造商:CPI 制造商全稱:CPI 功能描述:Magnetron |
| VMS1197B | 制造商:CPI 制造商全稱:CPI 功能描述:Magnetron |
| VMS128K8MB-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM Module |
| VMS128K8MC-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM Module |
| VMS128K8MF-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM Module |
發(fā)布緊急采購，3分鐘左右您將得到回復。