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參數(shù)資料
| 型號： | VMS115 |
| 元件分類： | 加密電路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 16/64頁 |
| 文件大?。?/td> | 572K |
| 代理商： | VMS115 |
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VLSI Technology, a subsidiary of Philips Semiconductors
8/10/99
23
Revision: 2.3
906
Data Sheet
5.3
External Interface
The SSRAM interface is the main interface between the security coprocessor chip, external mem-
ory and the external processor. Address, data, commands and control signals will flow through
this interface.
5.3.1
Register Summary
This section describes the registers required to interface with the security coprocessor.
WOC - Write one to clear.
5.3.1.1
Interrupt Status Register
The interrupt output is generated from the bitwise logical AND of the Interrupt Enable and Status
registers and a logical OR of the resulting bits. That is, if any bit in the resulting bitwise AND is
set, then an interrupt is generated. The interrupt output is active high and should be used as a level
sensitive interrupt by the host.
Bits 31-8
Reserved
Bit 7
Exponentiator Done - Exponentiator calculation is complete and output is ready.
This bit can be cleared in the Control/Status Register by setting Bit 7 to ‘0’.
0 - Exponentiation is not complete or has not been started.
1 - Exponentiation is complete.
Bit 6-5
Reserved
Bit 4
ORDY - Processed data is available to be read. This is equivalent to the ORDY
output pin. The ORDY output pin is not latched in this register.
0 - ORDY is low.
1 - ORDY is high.
Bit 3
IRDY - The VMS115 is ready to receive incoming data. This is equivalent to the
IRDY output pin. The IRDY output pin is not latched in this register.
0 - IRDY is low.
1 - IRDY is high.
Bit 2
Packet Done - Indicates the entire packet (Total Length in Opcode Register value)
External Interface Register Summary
Register
Address
Access
Description
Reset Value
Interrupt Status Register
0x400
R/WOC
Interrupt Status Register
00000000h
Interrupt Enable Register
0x401
R/W
Interrupt Enable Register
00000000h
Configuration Register
0x402
R/W
Configuration Register
00000000h
Interrupt Status Register Configuration
7
6
5
4
3
2
1
0
Expo Done
Reserved
ORDY
IRDY
Packet
Done
Hash Done
DES Done
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