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參數(shù)資料
| 型號： | VFC100 |
| 英文描述： | Synchronized VOLTAGE-TO-FREQUENCY CONVERTER |
| 中文描述： | 同步電壓頻率轉(zhuǎn)換器 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大小： | 205K |
| 代理商： | VFC100 |
VFC100
11
Clocked
Logic
Output
One-Shot
5
4
14
10
7
6
15
1
+V
CC
12
9
8
13
5V
Reference
16
+15VDC
0.1μF
+15VDC
–V
CC
–15VDC
0.1μF
0.1μF
C
1
1
1
0 to 10V
Input
Logic
Ground
f
O
= 0 to 100kHz
0.1μF
+V
L
4000 Counts
C
÷ 4000
(M = 4000)
D
Q
Q
68pF
22
22k
CMOS Inverters
Counter “N”
Maximum Count:
N = M/2 = 2000
To Processor
μP or Display
Computed Result
V
IN
' = 20V
x
(N/M)
Reset
R
IN
f
C
≈
200kHz
0.05μF
–V
CC
FIGURE 14. Diagram of a Voltage-to-Frequency Converter and Counter System.
R
IN
Clocked
Logic
Output
One-Shot
5
4
14
10
7
6
15
1
+V
CC
11
12
9
8
13
5V
Reference
16
–V
CC
–V
CC
+ 2 to +V
CC
– 2
–V
CC
+ 4 to +V
CC
– 2
> 3V
< 0.1V
> –7.5V
–V
CC
+ 4 to +V
CC
– 2
5V
+V
CC
or C
OS
> 7.5V
> –0.2V
7.5V to
28.5V
7.5V to 28.5V
–V
CC
+V
CC
–0.5V
to 30V
> 4V
> 2V
15V to
36V
–V
CC
FIGURE 13. Relationships of Allowable Voltages.
FREQUENCY-TO-VOLTAGE MODE
The VFC100 can also function as a frequency-to-voltage
converter by supplying an input frequency to the comparator
input as shown in Figure 16. The input resistor, R
IN
, is
connected as a feedback resistor. The voltage at the integra-
tor amp output is proportional to the ratio of the input
frequency to the clock frequency. The transfer function is
V
OUT
= (F
IN
/f
CLOCK
) 20V.
This transfer function is complementary to the voltage-to-
frequency mode transfer function, making voltage-to-fre-
quency-to-voltage conversions simple and accurate.
Direct coupling of the input frequency to the comparator is
easily accomplished by driving both comparators with
complementary frequency input signals. Alternatively, one
of the comparator inputs can be biased at half the logic
voltage (using V
REF
and a voltage divider) and the other
input driven directly.
The proper timing of the input frequency waveform is shown
in Figure 16. The input pulse should go low for one clock
cycle, centered around a falling edge of the clock. The
minimum acceptable input pulse width must fall no later
than 200ns before a negative clock edge and rise no sooner
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VFC100AG | Synchronized VOLTAGE-TO-FREQUENCY CONVERTER |
| VFC100BG | Synchronized VOLTAGE-TO-FREQUENCY CONVERTER |
| VFC101 | Synchronized VOLTAGE-TO-FREQUENCY CONVERTER |
| VFC101JN | Synchronized VOLTAGE-TO-FREQUENCY CONVERTER |
| VFC101KN | Synchronized VOLTAGE-TO-FREQUENCY CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VFC100AG | 制造商:BB 制造商全稱:BB 功能描述:Synchronized VOLTAGE-TO-FREQUENCY CONVERTER |
| VFC100BG | 制造商:BB 制造商全稱:BB 功能描述:Synchronized VOLTAGE-TO-FREQUENCY CONVERTER |
| VFC101 | 制造商:BB 制造商全稱:BB 功能描述:Synchronized VOLTAGE-TO-FREQUENCY CONVERTER |
| VFC101JN | 制造商:BB 制造商全稱:BB 功能描述:Synchronized VOLTAGE-TO-FREQUENCY CONVERTER |
| VFC101KN | 制造商:BB 制造商全稱:BB 功能描述:Synchronized VOLTAGE-TO-FREQUENCY CONVERTER |
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