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VFC100
10
R
IN
Clocked
Logic
Output
One-Shot
5
4
14
10
7
6
Clock
100kHz
15
1
+V
CC
11
12
9
8
13
5V
Reference
16
0.1μF
+8V
0.1μF
–V
CC
f
+V
L
C
INT
V
IN
–8V
0.1μF
+8V
V
TH
+ 100mV
V
TH
– 75mV
V
TH
2.25V
≈
Low Scale (V
Slow Oscilloscope Sweep
120mV)
≈
High Scale (V
Fast Oscilloscope Sweep
8.3V)
Integrator Voltage Waveform (Pin 4)
0.05μF
V
TH
2.25V
2.2k
1.8k
0 to 50kHz
0.1μF
0 to 10V
–V
CC
FIGURE 12. Circuit Diagram and Integrator Voltage Waveform Power Supply Voltage Operation.
clock period of the counting gate period. The quantizing
error can be made arbitrarily small by counting with long
gate times. For instance, a one-second counter gate period
with a 100kHz full-scale frequency has a resolution of one
part in 100,000. Many of the more sophisticated laboratory
frequency counters, however, use period measurement
schemes to count the input frequency quickly. These instru-
ments work equally well, but the gate period must be set
appropriately to achieve the desired count resolution. Short
gate periods will produce many digits of “accuracy” in the
display, but the results may be very inaccurate.
Figure 14 is a typical system application showing a basic
counting technique. A 0 to 10V input is converted to a 0 to
100kHz frequency output. The VFC’s clock is divided by M
= 4000 to produce a gate period for the counter circuit. The
resulting VFC count, N, is insensitive to variations in the
actual clock frequency. The input voltage represented by the
resulting count is V
IN
= (N/M) 20V.
Resolution is related to the number of counts at full scale, or
half the number of clock pulses in the gate period.
The integrating nature of the VFC is important in achieving
accurate conversions. The integrating period is equal to the
counting period. This can be used to great advantage to
reject unwanted signals of a known frequency. Figure 15
shows that response nulls occur at the inverse of the integra-
tion period and its multiples. If 60Hz is to be rejected, for
instance, the counting period should be made equal to, or a
multiple of, 1/60 of a second.
small, however, or the negative output limitation of the
integrator (–0.2V) may cause saturation. Additionally, a
large integrator capacitor may be used to limit the required
integrator waveform swing to approximately 100mV (see
“Integrator Capacitor”).
Figure 12 shows a circuit for operating from the minimum
power supplies, avoiding saturation of the integrator ampli-
fier and loss of accuracy. C
INT
is chosen for a +100mV to
–75mV integrator voltage swing (referred to the noninverting
comparator input). The offset voltage applied to the
comparator’s noninverting input is derived from a resistive
voltage divider from V
REF
.
The relationship of the allowable operating voltage ranges
on important pins is show in Figure 13. Note that the
integrator amplifier output cannot swing more than 0.2V
below ground. Although this is not “normal” for an opera-
tional amplifier, a special internal design of this type opti-
mizes high frequency performance. It is this characteristic
which necessitates the offsetting of the noninverting com-
parator input in voltage-to-frequency mode to avoid nega-
tive output swing.
COUNTING THE OUTPUT
In evaluation and use of the VFC100, you may want to
measure the output frequency with a frequency counter.
Since synchronization of the VFC100 causes it to await a
clock edge for any given output pulse, the output frequency
is essentially quantized. The quantized steps are equal to one