參數(shù)資料
型號(hào)： V62/05622-01XE
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： 12 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28
封裝： GREEN, PLASTIC, HTSSOP-28
文件頁(yè)數(shù)： 6/24頁(yè)
文件大?。?/td> 689K
代理商： V62/05622-01XE
www.ti.com
DETAILED DESCRIPTION
UNDERVOLTAGE LOCK OUT (UVLO)
SLOW-START/ENABLE (SS/ENA)
t
d +
C
(SS)
1.2 V
5 mA
(2)
t
(SS) +
C
(SS)
0.7 V
5 mA
(3)
VBIAS REGULATOR (VBIAS)
VOLTAGE REFERENCE
SGLS294A – FEBRUARY 2005 – REVISED AUGUST 2007
The TPS54610 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device
operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator and
a 2.5
μs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on
VIN.
The slow-start/enable pin provides two functions. First, the pin acts as an enable (shutdown) control by keeping
the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start-up begins. The reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-
μs falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
The second function of the SS/ENA pin provides an external means of extending the slow-start time with a
low-value capacitor connected between SS/ENA and AGND.
Adding a capacitor to the SS/ENA pin has two effects on start-up. First, a delay occurs between release of the
SS/ENA pin and start-up of the output. The delay is proportional to the slow-start capacitor value and lasts until
the SS/ENA pin reaches the enable threshold. The start-up delay is approximately:
Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor.
The slow-start time set by the capacitor is approximately:
The actual slow-start time is likely to be less than the above approximation due to the brief ramp-up at the
internal rate.
The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high-quality, low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over
temperature. The bypass capacitor must be placed close to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V,
and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be
useful as a reference voltage for external circuits.
The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the
high precision regulation of the TPS54610, since it cancels offset errors in the scale and error amplifier circuits.
14
Copyright 2005–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS54610-EP
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