參數(shù)資料
型號(hào)： V62/05622-01XE
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： 12 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28
封裝： GREEN, PLASTIC, HTSSOP-28
文件頁(yè)數(shù)： 21/24頁(yè)
文件大?。?/td> 689K
代理商： V62/05622-01XE
www.ti.com
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28
27
26
25
24
23
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21
20
19
18
17
16
15
AGND
VSENSE
COMP
PWRGD
BOOT
PH
RT
FSEL
SS/ENA
VBIAS
VIN
PGND
PWP PACKAGE
(TOP VIEW)
THERMAL
PAD
SGLS294A – FEBRUARY 2005 – REVISED AUGUST 2007
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and
AGND
1
FSEL pin. Connect PowerPAD to AGND.
Bootstrap output. 0.022-
μF to 0.1-μF low-ESR capacitor connected from BOOT to PH generates floating drive for the
BOOT
5
high-side FET driver.
COMP
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE.
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas
PGND
15–19
to the input and output supply returns, and negative terminals of the input and output capacitors. A single point
connection to AGND is recommended.
PH
6–14
Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
Power good open drain output. High when VSENSE
≥ 90% Vref, otherwise PWRGD is low. Note that output is low
PWRGD
4
when SS/ENA is low or the internal shutdown signal is active.
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using the
RT
28
FSEL pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency.
Slow-start/enable input/output. Dual function pin, which provides logic input to enable/disable device operation and
SS/ENA
26
capacitor input to externally set the start-up time.
Synchronization input. Dual function pin, which provides logic input to synchronize to an external oscillator or pin select
FSEL
27
between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be
connected to the RT pin.
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
VBIAS
25
high-quality, low-ESR 0.1-
μF to 1-μF ceramic capacitor.
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
VIN
20–24
device package with a high-quality, low-ESR 10-
μF ceramic capacitor.
VSENSE
2
Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
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Copyright 2005–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS54610-EP
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