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參數(shù)資料
| 型號： | V59C1G01408QAJ37I |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁數(shù)： | 52/79頁 |
| 文件大?。?/td> | 1029K |
| 代理商： | V59C1G01408QAJ37I |
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56
V59C1G01(408/808/168)QA Rev. 1.2 April 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
Self Refresh
L
X
Maintain Self Refresh
11, 15,16
L
H
DESELECT or NOP
Self Refresh Exit
4, 5, 9, 16
Bank(s) Active
H
L
DESELECT or NOP
Active Power Down Entry
4, 8, 10, 11, 13
All Banks Idle
H
L
DESELECT or NOP
Precharge Power Down Entry
4, 8, 10, 11,13
H
L
REFRESH
Self Refresh Entry
6, 9, 11,13
H
Refer to the Command Truth Table
7
NOTE 1
CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.
NOTE 2
Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
NOTE 3
COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
NOTE 4
All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
NOTE 5
On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR
period. Read commands may be issued only after tXSRD (200 clocks) is satisfied.
NOTE 6
Self Refresh mode can only be entered from the All Banks Idle state.
NOTE 7
Must be a legal command as defined in the Command Truth Table.
NOTE 8
Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
NOTE 9
Valid commands for Self Refresh Exit are NOP and DESELECT only.
NOTE 10
Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set oper-
ations or Precharge operations are in progress. See section 2.11 Power-down and 2.10 Self refresh operation for a detailed list of
restrictions.
NOTE 11
tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at
the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of tIS + 2 x tCK + tIH.
NOTE 12
The state of ODT does not affect the states described in this table. The ODT function is not available during Self
Refresh. See section 2.4.4.
NOTE 13
The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by
the refresh requirements outlined in section 2.9.
NOTE 14
CKE must be maintained HIGH while the SDRAM is in OCD calibration mode .
NOTE 15
“X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be
driven HIGH or LOW in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMR(1) ).
NOTE 16
VREF must be maintained during Self Refresh operation.
DM truth table
Name (Functional)
DM
DQs
Note
Write enable
LV alid
1
Write inhibit
HX
1
NOTE 1
Used to mask write data, provided coincident with the corresponding data
Clock enable (CKE) truth table for synchronous transitions
Current State 2
CKE
Command (N) 3
RAS, CAS, WE, CS
Action (N) 3
Notes
Previous Cycle 1
(N-1)
Current Cycle 1
(N)
Power Down
L
X
Maintain Power-Down
11, 13, 15
L
H
DESELECT or NOP
Power Down Exit
4, 8, 11,13
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