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參數(shù)資料
| 型號(hào)： | V59C1G01408QAJ37I |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁(yè)數(shù)： | 25/79頁(yè) |
| 文件大?。?/td> | 1029K |
| 代理商： | V59C1G01408QAJ37I |
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ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.2 April 2008
Burst Write Command
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined
by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) should be driven
low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins
at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write
cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is
completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ
signal is ignored after the burst write operation is complete. The time from the completion of the burst write to
bank precharge is named “write recovery time” (tWR) and is the time needed to store the write data into the
memory array. tWR is an analog timing parameter (see the AC table in this specification) and is not the pro-
grammed value for WR in the MRS.
Basic Burst Write Timing
DQS,
DQS
t DQSH
tDQSL
t WPRE
WPST
t
Din
t DS
t DH
Burst Write Operation : RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4
NOP
Precharge
NOP
WRITE A
Post CAS
T0
T2
T1
T3
T4
T5
T6
T7
Tn
WL = RL-1 = 4
BW543
CMD
DQ
NOP
DIN A0 DIN A1 DIN A2 DIN A3
<= tDQSS
tWR
Completion of
the Burst Write
DQS,
DQS
CK, CK
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