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參數(shù)資料
| 型號： | V59C1G01408QAJ37E |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁數(shù)： | 24/79頁 |
| 文件大?。?/td> | 1029K |
| 代理商： | V59C1G01408QAJ37E |
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30
V59C1G01(408/808/168)QA Rev. 1.2 April 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
Seamless Burst Read Operation : RL = 5, AL = 2, CL = 3, BL = 4
NOP
READ A
Post CAS
READ B
Post CAS
T0
T2
T1
T3
T4
T5
T6
T7
T8
Dout A0
Dout A1
Dout A2
Dout A3
Dout B0
Dout B1
Dout B2
Dout B3
RL = 5
AL = 2
CL = 3
SBR523
CMD
DQ
DQS,
DQS
CK, CK
The seamless burst read operation is supported by enabling a read command at every BL / 2 number of
clocks. This operation is allowed regardless of same or different banks as long as the banks are activated.
Seamless Burst Read Operation : RL = 3, AL = 0, CL = 3, BL = 8 (non interrupting)
NOP
READ A
Post CAS
T0
T2
T1
T3
T4
T5
T6
T7
T8
Dout A0
Dout A1
Dout A2
Dout A3
Dout A4
Dout A5
Dout A4
Dout A7
RL = 3
CL = 3
SBR_BL8
CMD
DQ
DQS,
DQS
READ B
Post CAS
Dout B0
Dout B1
Dout B2
Dout B3 Dou
NOP
NO
T9
CK, CK
The seamless, non interrupting 8-bit burst read operation is supported by enabling a read command at every
BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks
are activated.
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