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參數(shù)資料
| 型號(hào)： | V59C1G01408QAJ37E |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁(yè)數(shù)： | 15/79頁(yè) |
| 文件大?。?/td> | 1029K |
| 代理商： | V59C1G01408QAJ37E |
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V59C1G01(408/808/168)QA Rev. 1.2 April 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
ODT Timing for Active / Standby (Idle) Mode and Standard A c tive Power-Down Mode
ODT T iming for Prec harge Power-Down and L ow Power Power-Down Mode
1) B oth ODT to P ower Down Entry and E xit Latency timing parameter tANPD and tAXP D are met, therefore Non-P ower Down
Mode timings have to be applied.
2) ODT turn-on time (tAON,min) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on
time max. (tAON,max) is when the ODT resistance is fully on. B oth are measured from tAOND.
3) ODT turn off time min. ( tAOF,min) is when the device starts to turn off the ODT resistance.ODT turn off time max. (tAOF,max) is
when the bus is in high impedance. Both a re measured from tAOFD.
CKE
DQ
ODT1
ODT
CK, CK
T0
Rtt
t
IS
t
IS
tAON(min)
tAON(max)
tAOF(max)
tAOF(min)
t
IS
tAOND (2tck)
tAOFD (2.5 tck)
tANPD (>=3 tck)
tAXPD (>=8 tck)
t
IS
T-3
T-1
T-2
T-6
T-4
T-5
T-n
1) Both ODT to Power Down Entry and Exit Latencies tANPD and tAXPD are not met, therefore Power-Down Mode timings have to
be applied.
CKE
DQ
ODT
ODT2
CK, CK
t
IS
t
IS
tAOFP D,max
Rtt
tAONPD,min
tAOFP D,min
tAONP D,max
tANPD < 3 tck
tAXPD < 8 tck
T0
T1
T-1
T-2
T-3
T-5
T-4
T-6
T-7
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