參數(shù)資料
型號(hào)： V59C1G01408QAJ37E
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： 256M X 4 DDR DRAM, 0.5 ns, PBGA68
封裝： ROHS COMPLIANT, FBGA-68
文件頁數(shù)： 18/79頁
文件大小： 1029K
代理商： V59C1G01408QAJ37E
25
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.2 April 2008
Posted CAS
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in
DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immedi-
ately after the RAS bank activate command (or any time during the RAS to CAS delay time, tRCD, period).
The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read
Latency (RL) is the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a Read/Write
command before the tRCDmin, then AL greater than 0 must be written into the EMRS. The Write Latency
(WL) is always defined as RL - 1 (Read Latency -1) where Read Latency is defined as the sum of Additive
Latency plus CAS latency (RL=AL+CL). If a user chooses to issue a Read command after the tRCDmin
period, the Read Latency is also defined as RL = AL + CL.
Read followed by a write to the same bank, Activate to Read delay < tRCDmin:
AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4
Dout0 Dout1 Dout2Dout3
CMD
DQ
0
2
34
5
6
7
8
9
10
11
12
-1
1
tRCD
AL = 2
" tRAC"
RL = AL + CL = 5
CL = 3
WL = RL -1 = 4
Din0 Din1
Din2 Din3
PostCAS1
DQS,
DQS
Activate
Read
Write
Bank A
CK, CK
Read followed by a write to the same bank, Activate to Read delay < tRCDmin:
AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8
CMD
DQ
0
2
34
5
6
7
8
9
10
11
12
1
tRCD
AL = 2
" tRAC"
RL = AL + CL = 5
CL = 3
WL = RL -1 = 4
PostCAS3
DQS,
DQS
Activate
Read
Bank A
Din0 Din1
Din2 Din3
Write
Bank A
Dout0
Dout1
Dout2 Dout3
Dout0
Dout1
Dout2 Dout3
CK, CK
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PDF描述
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