- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄300083 > V58C2512804SALS5I (PROMOS TECHNOLOGIES INC) 64M X 8 DDR DRAM, 0.65 ns, PBGA60 PDF資料下載
參數(shù)資料
| 型號： | V58C2512804SALS5I |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 8 DDR DRAM, 0.65 ns, PBGA60 |
| 封裝： | MO-207, FBGA-60 |
| 文件頁數(shù)： | 36/60頁 |
| 文件大?。?/td> | 914K |
| 代理商： | V58C2512804SALS5I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當(dāng)前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
41
ProMOS TECHNOLOGIES
V58C2512(804/404/164)SA*I
V58C2512(804/404/164)SA*I Rev. 1.6 May 2007
Initial JEDEC specifications suggested this to be same as tDQSQ.
37. Normal Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage
will lie within the outer bounding lines of the V-I curve of Figure A.
b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but no
guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A.
c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie
within the outer bounding lines of the V-I curve of Figure B.
d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not
guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be
between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage
and temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device
drain-to-source voltages from 0.1V to 1.0 Volt.
38. Reduced Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage
will lie within the outer bounding lines of the V-I curve of Figure C.
b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not
guaranteed, to lie within the inner bounding lines of the V-I curve of Figure C.
c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie
within the outer bounding lines of the V-I curve of Figure D.
d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not
guaranteed, to lie within the inner bounding lines of the V-I curve of Figure D.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between
.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 V, and at the same voltage.
f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device
drain-to-source voltages from 0.1V to 1.0 V.
39. The voltage levels used are derived from the referenced test load. In practice, the voltage levels obtained from
a properly terminated bus will provide significantly different voltage values.
40. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3
of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width 3ns and the pulse width can not be greater than
1/3 of the cycle rate.
41. VDD and VDDQ must track each other.
42. Note 42 is not used.
43. Note 43 is not used.
44. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may
be 1.35V maximum during power up, even if VDD /VDDQ are 0 volts, provided a minimum of 42 ohms of series re-
sistance is used between the VTT supply and the input pin.
45. Note 45 is not used.
46. tRAP t RCD.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V58C2512404SAT5I | 128M X 4 DDR DRAM, 0.65 ns, PDSO66 |
| V59C1G01408QAJ37E | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
| V59C1G01408QAJ37I | 256M X 4 DDR DRAM, 0.5 ns, PBGA68 |
| V5D010EB4D | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.5A, 125VDC, 4.4mm, PANEL MOUNT |
| V5F110CB | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, PANEL MOUNT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V58C265164S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:64 Mbit DDR SDRAM 2.5 VOLT 4M X 16 |
| V58C265404S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4 |
| V58C265804S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8 |
| V58C3643204SAT | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 3.3 VOLT 2M X 32 DDR SDRAM 4 X 512K X 32 |
| V58C365164S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:64 Mbit DDR SDRAM 4M X 16, 3.3VOLT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。