參數(shù)資料
型號: V55C3256164VBLG8
廠商: PROMOS TECHNOLOGIES INC
元件分類: DRAM
英文描述: SYNCHRONOUS DRAM, PBGA54
封裝: ROHS COMPLIANT, MO-210, FBGA-54
文件頁數(shù): 6/46頁
文件大小: 575K
代理商: V55C3256164VBLG8
14
V55C3256164VB Rev. 1.0 March 2008
ProMOS TECHNOLOGIES
V55C3256164VB
AC Characteristics 1,2, 3
TA = 0 to 70 °C(Commercial)/-40 to 85 °C(Industrial);VSS = 0 V; VCC ,VCCQ= (3V~3.3V)+/- 0.3V tT=1 ns
#
Symbol Parameter
Limit Values
Unit
Note
-7
-10
Min.
Max.
Min.
Max.
Clock and Clock Enable
1tCK
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
7
10
20
10
12
25
ns
2tCK
Clock Frequency
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
143
100
50
100
83
40
MHz
3tAC
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
_
5.4
6
19
_
7
8
22
ns
2, 4
4tCH
Clock High Pulse Width
2.5
3
ns
5tCL
Clock Low Pulse Width
2.5
3
ns
6tT
Transition Tim
0.3
1.2
0.5
10
ns
Setup and Hold Times
7tIS
Input Setup Time
1.5
2.5
ns
5
8tIH
Input Hold Time
0.8
1
ns
5
9tCKS
Input Setup Time
1.5
2.5
ns
5
10
tCKH
CKE Hold Time
0.8
1
ns
5
11
tRSC
Mode Register Set-up Time
14
20
ns
12
tSB
Power Down Mode Entry Time
0
7
0
8
ns
Common Parameters
13
tRCD
Row to Column Delay Time
15
20
ns
6
14
tRP
Row Precharge Time
15
20
ns
6
15
tRAS
Row Active Time
42
100K
50
100k
ns
6
16
tRC
Row Cycle Time
60
70
ns
6
17
tRRD
Activate(a) to Activate(b) Command Period
14
20
ns
6
18
tCCD
CAS(a) to CAS(b) Command Period
1
1
CLK
Refresh Cycle
19
tREF
Refresh Period (8192 cycles)
64
64
ms
20
tSREX
Self Refresh Exit Time
1
1
CLK
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