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參數(shù)資料
| 型號(hào)： | V29LC51002 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 2 MEGABIT 262,144 x 8 BIT 5 VOLT CMOS FLASH MEMORY |
| 中文描述： | 2兆位262,144 × 8位5伏的CMOS閃存 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 52K |
| 代理商： | V29LC51002 |
8
V29LC51002 Rev. 0.5 October 2000
MOSEL V ITELIC
V29LC51002
FUNCTIONAL DESCRIPTION
Read Cycle
A read cycle is performed by holding both CE
and OE signals LOW. Data Out becomes valid only
when these conditions are met. During a read cycle
WE must be HIGH prior to CE and OE going LOW.
WE must remain HIGH during the read operation
for the read to complete (see Table 1).
Output Disable
Returning OE or CE HIGH, whichever occurs first
will terminate the read operation and place the l/O
pins in the HIGH-Z state.
Standby
The device will enter standby mode when the CE
signal is HIGH. The l/O pins are placed in the
HIGH-Z, independent of the OE input state.
Command Sequence
The V29LC51002 does not provide the
“
reset
”
feature to return the chip to its normal state when
an incomplete command sequence or an
interruption has happened. In this case, normal
operation (Read Mode) can be restored by issuing
a
“
non-existent
”
command sequence, for example
Address: 5555H, Data FFH.
Byte Write Cycle
The V29LC51002 is programmed on a byte-by-
byte basis. The byte write operation is initiated by
using a specific four-bus-cycle sequence: two
unlock program cycles, a program setup command
and program data program cycles (see Table 2).
During the byte write cycle, addresses are
latched on the falling edge of either CE or WE,
whichever is last. Data is latched on the rising edge
of CE or WE, whichever is first. The byte write cycle
can be CE controlled or WE controlled.
Sector Erase Cycle
The V29LC51002 features a sector erase
operation which allows each sector to be erased
and reprogrammed without affecting data stored in
other sectors. Sector erase operation is initiated by
using a specific six-bus-cycle sequence: Two
unlock program cycles, a setup command, two
additional unlock program cycles, and the sector
erase command (see Table 2). A sector must be
first erased before it can be re-written. While in the
internal erase mode, the device ignores any
program attempt into the device. Sector erase is
completed in 10ms max. The V29LC51002 is
shipped fully erased (all bits = 1).
512
512
512
512
V29LC51002
00000H
C51002-15
Table 1. Operation Modes Decoding
NOTES:
1.
2.
X = Don
’
t Care, V
IH
= HIGH, V
IL
= LOW, V
H
= 12.5V Max.
PD: The data at the byte address to be programmed.
Decoding Mode
Read
Byte Write
Standby
Output Disable
CE
V
IL
V
IL
V
IH
V
IL
OE
V
IL
V
IH
X
V
IH
WE
V
IH
V
IL
X
V
IH
A
0
A
0
A
0
X
X
A
1
A
1
A
1
X
X
A
9
A
9
A
9
X
X
I/O
READ
PD
HIGH-Z
HIGH-Z
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