- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄359317 > V292BMC-33LP (Electronic Theatre Controls, Inc.) HIGH PERFORMANCE BURST DRAM CONTROLLER FOR Am29030/40 PROCESSORS PDF資料下載
參數(shù)資料
| 型號(hào)： | V292BMC-33LP |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HIGH PERFORMANCE BURST DRAM CONTROLLER FOR Am29030/40 PROCESSORS |
| 中文描述： | 爆高性能的DRAM控制器的Am29030/40處理器 |
| 文件頁(yè)數(shù)： | 4/14頁(yè) |
| 文件大?。?/td> | 100K |
| 代理商： | V292BMC-33LP |
第1頁(yè)第2頁(yè)第3頁(yè)當(dāng)前第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)
V292BMC Rev.D
4
V292BMC Rev D Data Sheet Rev 3.2
Copyright 1998, V3 Semiconductor Inc.
Signal
Type
R
Description
A[31:2]
I
Local address bus.
ALE
I
Address Latch Enable: controls a set of transparent latches on the
address bus. When asserted high, the address input flows through
the latch. When ALE is low, the internal address holds the previous
value. With an Am29030/40 processor ALE is not typically used and
has an internal pull-up resistor that will keep it high when not con-
nected (to provide backward pin compatibility with earlier versions).
I/D
I
Data/Code.
BWE[3:0]
I
Local bus byte write enables.
R/W
I
Read/write.
REQ
I
Asserted low to indicate the beginning of a bus cycle.
RDY
O
12
Z
Local bus data ready.
PRDY
I
Processor ready
SUP/US
I
Indicates supervisor mode. Required for access to configuration reg-
isters.
BURST
I
Burst request.
ERR
O
12
H
Bus Time-out error.
INT
O
12
H
Local interrupt request. This signal is asserted when the 24-bit
counter reaches terminal count, and interrupt out is enabled. May
be programmed for pulse or level operation.
RESET
I
Local bus reset signal.
MEMCLK
I
Local bus clock.
ID[2:0]
I
These inputs select the address offset of the configuration registers.
Power and Ground Signals
Signal
Type
R
Description
Vcc
-
POWER leads intended for external connection to a 5V Vcc plane
Vcc3
-
POWER for DRAM control outputs. Can be connected to 3.3V or 5V.
GND
-
GROUND leads intended for external connection to a GND plane.
a.
R
indicates state during reset.
Table 3: Signal Descriptions (cont’d)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V292BMC | HIGH PERFORMANCE BURST DRAM CONTROLLER FOR Am29030/40 PROCESSORS |
| V29C31001B-70P | 1 MEGABIT 131,072 x 8 BIT 5 VOLT CMOS FLASH MEMORY |
| V29C31004B | 4 MEGABIT 524,288 x 8 BIT 3.3 VOLT CMOS FLASH MEMORY |
| V29C51000B | 512K Bit 5 Volt CMOS Flash Memory(512K位5V CMOS閃速存儲(chǔ)器) |
| V29C51000T-90P | 512K BIT 65,536 x 8 BIT 5 VOLT CMOS FLASH MEMORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V292BMC-40LP | 制造商:Rochester Electronics LLC 功能描述: 制造商:QuickLogic Corporation 功能描述: |
| V292PBC-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bus Interface/Controller |
| V292PBC-33LP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bus Interface/Controller |
| V292PBC-40 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bus Interface/Controller |
| V292PBC-40LP | 制造商:QuickLogic Corporation 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。