參數(shù)資料
型號(hào): V292BMC-33LP
廠商: Electronic Theatre Controls, Inc.
英文描述: HIGH PERFORMANCE BURST DRAM CONTROLLER FOR Am29030/40 PROCESSORS
中文描述: 爆高性能的DRAM控制器的Am29030/40處理器
文件頁數(shù): 11/14頁
文件大?。?/td> 100K
代理商: V292BMC-33LP
V292BMC Rev.D
Copyright 1998, V3 Semiconductor Corp.
V292BMC Rev D Data Sheet Rev 3.2
11
NOTES:
1. Specified from MEMCLK falling edge.
2. t
= t
when T_MUX = 1; t
= 0.5
t
when T_MUX = 0.
3. Maximum RAS pulse width depends on the number of burst access.
4. t
N
= 1.5
t
when T_RAS = 0; t
N
= 2.5
t
when T_RAS = 1.
5. t
= 2
t
when T_RAS = 0; t
= 2
t
when T_RAS = 1 and T_RP = 1;
t
= 3
t
when T_RAS = 1 and T_RP = 0.
6. Rising delay is measured from MEMCLK falling edge, falling delay is measured from MEMCLK rising edge.
7. Except for Mode 2 and 3 at TXA pin.
8. In order to have 3.3 Volt DRAM interface Vcc3 pins must be connected to 3.3 Volt.
Vcc3 pins are: PIN # 91, 97, 103, 57, 63, 69, 75, 81.
The power supply pins that must always be connected to 5 Volt are Vcc.
Vcc pins are: PIN # 4, 47, 115.
Figure 3: Clock and Synchronous Signals
t
CLH
t
CAS
t
CPN
t
RCD
t
WESU
t
WEH
t
LED
t
TXHL1
t
TXHL2
MEMCLK to CAS de-asserted delay
4
12
3
11
ns
CAS pulse width
4
t
N
-1
0.5t
C
t
N
-1
0.5t
C
ns
CAS precharge time
ns
RAS to CAS delay time
1.5t
C
-2
1.5t
C
1.5t
C
-2
1.5t
C
ns
Write Enable setup to RAS assertion
10
9
ns
Write Enable hold from RAS de-assertion
1
3
1
3
ns
MEMCLK to Latch Enable output delay
6
3
12
3
10
ns
MEMCLK to Buffer Control fall delay
7
3
13
3
11
ns
MEMCLK to Buffer Control fall delay (Mode 2
and 3 at TXA pin only)
4
15
4
13
ns
t
TXLH
t
RFHL
t
RFLH
t
ASU
t
AH
MEMCLK to Buffer Control rise delay
3
12
3
10
ns
REFRESH synchronous assertion delay
3
13
3
11
ns
REFRESH synchronous de-assertion delay
3
13
3
11
ns
Address setup to ALE Falling
6
5
ns
Address hold from ALE Falling
5
4
ns
Table 11: Timing Parameters for V292BMC Vcc = 5 Volts +/- 5% (cont’d)and
Vcc3 = 5 or 3.3
8
Volts +/- 5%
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