參數(shù)資料
型號: USB3450
廠商: SMSC Corporation
英文描述: HI-SPEED USB HOST OR DEVICE PHY WITH UTMI+INTERFACE
中文描述: 高速USB主機或設備與UTMI接口物理層
文件頁數(shù): 20/40頁
文件大?。?/td> 1086K
代理商: USB3450
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
Revision 0.1 (05-11-05)
20
SMSC USB3450
DATASHEET
Chapter 6 Detailed Functional Overview
Figure 2.1 on page 9
shows the functional block diagram of the USB3450. Each of the functions is
described in detail below.
6.1
8bit Bi-Directional Data Bus Operation
The USB3450 supports an 8-bit bi-directional parallel interface.
CLKOUT runs at 60MHz
The 8-bit data bus (DATA[7:0]) is used for transmit when TXVALID = 1
The 8-bit data bus (DATA[7:0]) is used for receive when TXVALID = 0
Figure 6.1
shows the relationship between CLKOUT and the transmit data transfer signals in FS mode.
TXREADY is only asserted for one CLKOUT per byte time to signal the Link that the data on the DATA
lines has been read by the PHY. The Link may hold the data on the DATA lines for the duration of the
byte time. Transitions of TXVALID must meet the defined setup and hold times relative to CLKOUT.
Figure 6.2
shows the relationship between CLKOUT and the receive data control signals in FS mode.
RXACTIVE “frames” a packet, transitioning only at the beginning and end of a packet. However
transitions of RXVALID may take place any time 8 bits of data are available.
Figure 6.2
also shows
how RXVALID is only asserted for one CLKOUT cycle per byte time even though the data may be
presented for the full byte time. The XCVRSELECT signal determines whether the HS or FS timing
relationship is applied to the data and control signals.
Figure 6.1 FS CLK Relationship to Transmit Data and Control Signals
Figure 6.2 FS CLK Relationship to Receive Data and Control Signals
相關PDF資料
PDF描述
USB3450-FZG HI-SPEED USB HOST OR DEVICE PHY WITH UTMI+INTERFACE
USB97C201 USB 2.0 ATA/ ATAPI Controller
USB97C201-MC USB 2.0 ATA/ ATAPI Controller
USB97C201-MN USB 2.0 ATA/ ATAPI Controller
USB97CFDC-MN USB FLOPPY DISK CONTROLLER
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