參數(shù)資料
型號(hào)： UPD784216AGC-XXX-8EU
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 12.5 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, PLASTIC, LQFP-100
文件頁數(shù)： 20/35頁
文件大?。?/td> 6047K
代理商： UPD784216AGC-XXX-8EU
27
User’s Manual U13570EJ3V1UD
LIST OF FIGURES (7/8)
Figure No.
Title
Page
23-34
Single-Phase Excitation of 4-Phase Stepping Motor .............................................................................. 463
23-35
1-2-Phase Excitation of 4-Phase Stepping Motor ................................................................................... 463
23-36
Automatic Addition Control + Ring Control Block Diagram 1
(When Output Timing Varies with 1-2-Phase Excitation) ........................................................................ 464
23-37
Automatic Addition Control + Ring Control Timing Diagram 1
(When Output Timing Varies with 1-2-Phase Excitation) ........................................................................ 465
23-38
Automatic Addition Control + Ring Control Block Diagram 2
(1-2-Phase Excitation Constant-Velocity Operation) ............................................................................... 466
23-39
Automatic Addition Control + Ring Control Timing Diagram 2
(1-2-Phase Excitation Constant-Velocity Operation) ............................................................................... 467
23-40
Macro Service Data Transfer Processing Flow (Counter Mode) ............................................................. 468
23-41
Counter Mode ......................................................................................................................................... 469
23-42
Counting Number of Edges ..................................................................................................................... 469
23-43
Interrupt Request Generation and Acknowledgment (Unit: Clock = 1/fCLK) ............................................. 471
24-1
Memory Expansion Mode Register (MM) Format ................................................................................... 479
24-2
External Bus Type Selection Register (EBTS) Format ........................................................................... 480
24-3
Programmable Wait Control Register (PWC1) Format ........................................................................... 480
24-4
PD784214A Memory Map ..................................................................................................................... 483
24-5
PD784215A Memory Map ..................................................................................................................... 485
24-6
PD784216A Memory Map ..................................................................................................................... 487
24-7
PD784217A Memory Map ..................................................................................................................... 489
24-8
PD784218A Memory Map ..................................................................................................................... 491
24-9
Instruction Fetch from External Memory in Multiplexed Bus Mode ......................................................... 494
24-10
Read Timing for External Memory in Multiplexed Bus Mode .................................................................. 495
24-11
Write Timing for External Memory in Multiplexed Bus Mode .................................................................. 496
24-12
Read Modify Write Timing for External Memory in Multiplexed Bus Mode ............................................. 497
24-13
Instruction Fetch from External Memory in Separate Bus Mode ............................................................ 499
24-14
Read Timing for External Memory in Separate Bus Mode ...................................................................... 500
24-15
Write Timing for External Memory in Separate Bus Mode ...................................................................... 501
24-16
Read Modify Write Timing for External Memory in Separate Bus Mode ................................................. 503
24-17
Read/Write Timing by Address Wait Function ......................................................................................... 504
24-18
Read Timing by Access Wait Function .................................................................................................... 507
24-19
Write Timing by Access Wait Function .................................................................................................... 509
24-20
Timing by External Wait Signal ............................................................................................................... 511
24-21
Configuration of External Access Status Output Function ...................................................................... 512
24-22
External Access Status Enable Register (EXAE) Format ....................................................................... 513
24-23
Example of Local Bus Interface .............................................................................................................. 515
25-1
Standby Function State Transitions ........................................................................................................ 517
25-2
Standby Control Register (STBC) Format .............................................................................................. 519
25-3
Clock Status Register (PCS) Format ...................................................................................................... 521
25-4
Oscillation Stabilization Time Specification Register (OSTS) Format ..................................................... 523
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