參數(shù)資料
型號: UPD784216AGC-XXX-8EU
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 12.5 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, PLASTIC, LQFP-100
文件頁數(shù): 18/35頁
文件大?。?/td> 6047K
代理商: UPD784216AGC-XXX-8EU
25
User’s Manual U13570EJ3V1UD
LIST OF FIGURES (5/8)
Figure No.
Title
Page
17-5
Baud Rate Generator Control Registers 1, 2 (BRGC1, BRGC2) Format ............................................... 302
17-6
Baud Rate Capacity Error Considering Sampling Errors (When k = 0) .................................................. 309
17-7
Asynchronous Serial Interface Transmit/Receive Data Format .............................................................. 310
17-8
Asynchronous Serial Interface Transmit Completion Interrupt Timing .................................................... 312
17-9
Asynchronous Serial Interface Receive Completion Interrupt Timing ..................................................... 313
17-10
Receive Error Timing .............................................................................................................................. 314
17-11
Comparison of Infrared Data Transfer Mode and UART Mode Data Formats ........................................ 315
17-12
Block Diagram in 3-Wire Serial I/O Mode ............................................................................................... 320
17-13
Serial Operation Mode Registers 1, 2 (CSIM1, CSIM2) Format ............................................................. 321
17-14
Serial Operation Mode Registers 1, 2 (CSIM1, CSIM2) Format ............................................................. 322
17-15
Serial Operation Mode Registers 1, 2 (CSIM1, CSIM2) Format ............................................................. 323
17-16
3-Wire Serial I/O Mode Timing ................................................................................................................ 324
18-1
Block Diagram of Clocked Serial Interface (in 3-Wire Serial I/O Mode) ................................................. 326
18-2
Serial Operation Mode Register 0 (CSIM0) Format ................................................................................ 327
18-3
Serial Operation Mode Register 0 (CSIM0) Format ................................................................................ 329
18-4
Serial Operation Mode Register 0 (CSIM0) Format ................................................................................ 330
18-5
3-Wire Serial I/O Mode Timing ................................................................................................................ 331
19-1
Serial Bus Configuration Example in I2C Bus Mode ............................................................................... 333
19-2
Block Diagram of Clocked Serial Interface (I2C Bus Mode) .................................................................... 334
19-3
I2C Bus Control Register (IICC0) Format ................................................................................................ 337
19-4
I2C Bus Status Register (IICS0) Format .................................................................................................. 341
19-5
Format of Prescaler Mode Register for Serial Clock (SPRM0) ............................................................... 345
19-6
Pin Configuration .................................................................................................................................... 347
19-7
Serial Data Transfer Timing of I2C Bus ................................................................................................... 348
19-8
Start Condition ........................................................................................................................................ 348
19-9
Address ................................................................................................................................................... 349
19-10
Transfer Direction Specification .............................................................................................................. 349
19-11
Acknowledge Signal ................................................................................................................................ 350
19-12
Stop Condition ........................................................................................................................................ 351
19-13
Wait Signal .............................................................................................................................................. 352
19-14
Example of Arbitration Timing ................................................................................................................. 375
19-15
Timing of Communication Reservation ................................................................................................... 378
19-16
Communication Reservation Acceptance Timing .................................................................................... 378
19-17
Communication Reservation Procedure ................................................................................................. 379
19-18
Master Operating Procedure ................................................................................................................... 381
19-19
Slave Operating Procedure ..................................................................................................................... 382
19-20
Master
→ Slave Communication Example (When Master and Slave Select 9 Clock Waits) .................. 384
19-21
Slave
→ Master Communication Example (When Master and Slave Select 9 Clock Waits) .................. 387
20-1
Remote Control Output Application Example .......................................................................................... 390
20-2
Clock Output Function Block Diagram .................................................................................................... 391
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