參數(shù)資料
型號(hào)： UPD75P216A
廠商： NEC Corp.
英文描述： 4-BIT SINGLE-CHIP MICROCOMPUTER
中文描述： 4位單片機(jī)
文件頁(yè)數(shù)： 20/28頁(yè)
文件大?。?/td> 281K
代理商： UPD75P216A
μ
PD75P216A
20
DC Programming Characteristics (T
a
= 25
±
5
°
C, V
DD
= 6.0
±
0.25 V, V
PP
= 12.5
±
0.3 V, V
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
IH1
All except X1, X2
0.7 V
DD
V
DD
V
V
IH2
X1, X2
V
DD
–0.5
V
DD
V
V
IL1
All except X1, X2
0
0.3 V
DD
V
V
IL2
X1, X2
0
0.4
V
Input leakage current
I
L1
V
IN
= V
IL
or V
IH
10
μ
A
High-level output voltage
V
OH
I
OH
= –1 mA
V
DD
–1.0
V
Low-level output voltage
V
OL
I
OL
= 1.6 mA
0.4
V
V
DD
power supply current
I
DD
30
mA
V
PP
power supply current
I
PP
MD0 = V
IL
, MD1 = V
IH
30
mA
Note 1.
V
PP
should not exceed +22 V (including overshoot).
2.
V
DD
should be applied before V
PP
and turned off after V
PP
.
AC Programming Characteristics (T
a
= 25
±
5
°
C, V
DD
= 6.0
±
0.25 V, V
PP
= 12.5
±
0.3 V, V
SS
= 0 V)
Parameter
Symbol
Note 1
Conditions
MIN.
TYP.
MAX.
Unit
Address setup time
Note 2
(toMD0
↓
)
MD1 setup time (to MD0
↓
)
t
AS
t
AS
2
μ
s
μ
s
μ
s
μ
s
μ
s
t
MIS
t
OES
2
Data setup time
(to MD0
↓
)
t
DS
t
DS
2
Address hold time
Note 2
(from MD0
↑
)
t
AH
t
AH
2
Data hold time
(from MD0
↑
)
t
DH
t
DH
2
MD0
↑
→
data output float delay time
t
DF
t
DF
0
130
ns
V
PP
setup time
(to MD3
↑
)
(to MD3
↑
)
t
VPS
t
VPS
2
μ
s
μ
s
V
DD
setup time
t
VDS
t
VCS
2
Initialized program pulse width
t
PW
t
PW
0.95
1.0
1.05
ms
Additional program pulse width
t
OPW
t
OPW
0.95
21.0
ms
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
MD0 setup time
MD0
↓ →
data output delay time
(to MD1
↑
)
t
MOS
t
CES
2
t
DV
t
DV
MD0 = MD1 = V
IL
1
MD1 hold time
(from MD0
↑
)
(to MD0
↓
)
t
MIH
t
OEH
2
MD1 recovery time
t
MIR
t
OR
2
Program counter reset time
t
PCR
—
10
X1 input high- and low-level width
t
XH
, t
XL
—
0.125
X1 input frequency
f
X
—
4.19
MHz
μ
s
μ
s
μ
s
μ
s
μ
s
Initial mode set time
t
I
—
2
MD3 setup time
(to MD1
↑
)
(from MD1
↓
)
(to MD0
↓
)
t
M3S
—
2
MD3 hold time
t
M3H
—
2
MD3 setup time
t
M3SR
—
During program read cycle
2
Address
Note 2
→
Data output delay time
Address
Note 2
→
Data output hold time
MD3 hold time
t
DAD
t
ACC
During program read cycle
2
t
HAD
t
OH
During program resd cycle
0
130
ns
μ
s
μ
s
(from MD0
↑
)
t
M3HR
—
During program read cycle
2
MD3
↓ →
data output float delay time
t
DFR
—
During program read cycle
2
Note 1.
Symbol of corresponding
μ
PD27C256.
2.
Internal address is incremented by 1 at the rising edge of the fourth X1 input. This address signal
is not output to external pins.
t
MIH
+ t
MIR
≥
50
μ
s
High-level input voltage
Low-level input voltage
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