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參數(shù)資料
| 型號： | UPD75P216A |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機 |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 281K |
| 代理商： | UPD75P216A |
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μ
PD75P216A
19
Data Memory STOP Mode Low Voltage Data Retention Characteristics (T
a
= –10 to +70
°
C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data retention voltage
V
DDDR
2.0
5.5
V
Data retention current
I
DDDR
V
DDDR
= 2.0 V
0.1
10
μ
A
Released signal SET time
t
SREL
0
μ
s
Released by RESET input
2
17
/f
X
ms
Released by interrupt request
Note 2
ms
Note 1.
The oscillation stabilization wait time is a period during which the CPU is kept inactive in order to
avoid unstable operation at the start of oscillation.
2.
Depends on the setting of the basic interval time mode register (BTM) (see the following table).
BTM3
BTM2
BTM1
BTM0
Wait time ( ): f
XX
= 4.19 MHz
—
0
0
0
2
20
/f
XX
(approx. 250 ms)
—
0
1
1
2
17
/f
XX
(approx. 31.3 ms)
—
1
0
1
2
15
/f
XX
(approx. 7.82 ms)
—
1
1
1
2
13
/f
XX
(approx. 1.95 ms)
Data Retention Timing (STOP mode is released by RESET input)
Data Retention Timing (Standby release signal: STOP mode is released by interrupt signal)
Note 1
Oscillation stabilization time
t
WAIT
V
DD
RESET
V
DD
Standby release signal
(interrupt request)
Execution of STOP instruction
Execution of STOP instruction
Internal reset operation
HALT mode
Operation mode
HALT mode
Operation mode
STOP mode
Data retention mode
V
DDDR
t
SREL
t
WAIT
STOP mode
Data retention mode
V
DDDR
t
SREL
t
WAIT
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