參數(shù)資料
型號(hào)： UPD75P116CW
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, SHRINK, PLASTIC, DIP-64
文件頁(yè)數(shù)： 15/32頁(yè)
文件大?。?/td> 286K
代理商： UPD75P116CW
22
PD75P116
STOP Instruction Execution
VDD
VDDDR
Standby Release Signal
(Interrupt Request)
Operating Mode
HALT Mode
STOP Mode
Data Retention Mode
tWAIT
tSREL
STOP Instruction Execution
VDD
VDDDR
RESET
Operating Mode
HALT Mode
Internal RESET Operation
STOP Mode
Data Retention Mode
tWAIT
tSREL
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to
+85
°C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data retention supply voltage
VDDDR
2.0
5.5
V
Data retention power supply current *1
IDDDR
VDDDR = 2.0 V
0.1
10
A
Release signal set time
tSREL
0
s
Release by RESET
217/fx
ms
Release by interrupt request
*3
ms
Oscillation stabilization wait time *2
tWAIT
*1.
Does not include current flowing in the comparator.
2.
The oscillator stabilization wait time is the time during which CPU operation is halted to prevent
unstable operation when oscillation begins.
3.
Depends on the setting of the basic interval timer mode register (BTM) (table below).
BTM3 BTM2 BTM1 BTM0
WAIT Time (Figure in Parentheses is for fXX = 4.19 MHz)
–
000
220/fXX (Approx. 250 ms)
–
011
217/fXX (Approx. 31.3 ms)
–
101
215/fXX (Approx. 7.82 ms)
–
111
213/fXX (Approx. 1.95 ms)
Data Retention Timing (STOP Mode Release by RESET)
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
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