參數(shù)資料
型號(hào)： UPD75P116CW
元件分類(lèi)： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, SHRINK, PLASTIC, DIP-64
文件頁(yè)數(shù)： 11/32頁(yè)
文件大?。?/td> 286K
代理商： UPD75P116CW
19
PD75P116
tCY vs. VDD
Cycle
Time
t
CY
[
s]
Supply Voltage VDD [V]
Operating
Guaranteed
Range
10
5
1
0.5
0
1
2
3
4
5
6
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD = 4.75 to 5.5 V
0.95
32
s
1.1
32
s
fTI
0
1
MHz
tTIH,
0.48
s
tTIL
tKCY
Input
0.8
s
Output
0.95
s
tKH,
Intput
0.4
s
tKL
Output
tKCY/2–50
ns
tSIK
100
ns
tKSI
400
ns
tKSO
300
ns
5
s
tRSL
5
s
AC CHARACTERISTICS (Ta = –40 to +85
°C, VDD = 2.7 to 6.0 V)
tCY
PARAMETER
CPU clock cycle time*
(minimum instruction
execution time = 1 ma-
chine cycle)
TI input frequency
TI input high/low-level
width
SCK cycle time
SCK high/low-level width
SI setup time (to SCK
↑)
SI hold time (from SCK
↑)
SO output delay time
from SCK
↓
INT0 to INT4 high/low-
level width
RESET low level width
tINTH,
tINTL
*
The cycle time of the CPU clock (
Φ) is determined by the oscillator frequency of the connected resonator
and the processor clock control register (PCC).
The graph on the below shows the cycle time tCY characteristics against supply voltage VDD.
Relation between Cycle Time and Supply Voltage
Note tCY vs. VDD characteristics are different from those of the
PD75P108
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