
84
PD753104, 753106, 753108
Data Sheet U10086EJ5V1DS
APPENDIX A.
PD75308B, 753108 AND 75P3116 FUNCTIONAL LIST
Parameter
PD75308B
PD753108
PD75P3116
Program memory
Mask ROM
One-time PROM
0000H to 1F7FH
0000H to 1FFFH
0000H to 3FFFH
(8064
× 8 bits)
(8192
× 8 bits)
(16384
× 8 bits)
Data memory
000H to 1FFH
(512
× 4 bits)
CPU
75X Standard
75XL CPU
Instruction
When main system clock is
0.95, 1.91, 15.3
s 0.95, 1.91, 3.81, 15.3 s (during 4.19 MHz operation)
execution
selected
(during 4.19 MHz operation)
0.67, 1.33, 2.67, 10.7
s (during 6.0 MHz operation)
time
When subsystem clock is
122
s (during 32.768 kHz operation)
selected
Stack
SBS register
None
SBS.3 = 1: Mk I mode selection
SBS.3 = 0: Mk II mode selection
Stack area
000H to 0FFH
000H to 1FFH
Subroutine call instruction
2-byte stack
When Mk I mode: 2-byte stack
stack operation
When Mk II mode: 3-byte stack
Instruction
BRA !addr1
Unavailable
When Mk I mode: unavailable
CALLA !addr1
When Mk II mode: available
MOVT XA, @BCDE
Available
MOVT XA, @BCXA
BR BCDE
BR BCXA
CALL !addr
3 machine cycles
Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles
CALLF !faddr
2 machine cycles
Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles
I/O port
CMOS input
8
CMOS input/output
16
20
Bit port output
8
0
N-ch open-drain input/output
84
Total
40
32
LCD controller/driver
Segment selection: 24/28/32
Segment selection: 16/20/24 segments
segments
(can be changed to CMOS input/output port in 4 time-unit;
(can be changed to CMOS
max. 8)
input/output port in 4 time-
unit; max. 8)
Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias),
1/4 duty (1/3 bias)
On-chip split resistor for LCD driver can be specified by using
No on-chip split resistor for
mask option.
LCD driver
Timer
3 channels
5 channels
Basic interval timer:
Basic interval timer/watchdog timer: 1 channel
1 channel
8-bit timer/event counter: 3 channels
8-bit timer/event counter:
(can be used as 16-bit timer/event counter)
1 channel
Watch timer: 1 channel