參數(shù)資料
型號(hào)： UPD753108GK-XXX-9ET
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝： 12 X 12 MM, PLASTIC, TQFP-64
文件頁數(shù)： 69/100頁
文件大?。?/td> 736K
代理商： UPD753108GK-XXX-9ET
68
PD753104, 753106, 753108
Data Sheet U10086EJ5V1DS
AC CHARACTERISTICS (TA = –40 to +85C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
CPU clock cycle
tCY
Operating on
VDD = 2.7 to 5.5 V
0.67
64
s
timeNote 1
main system clock
VDD = 1.8 to 5.5 V
0.95
64
s
(minimum instruction execution
Operating on subsystem clock
114
122
125
s
time = 1 machine cycle)
TI0, TI1, TI2 input
fTI
VDD = 2.7 to 5.5 V
0
1.0
MHz
frequency
VDD = 1.8 to 5.5 V
0
275
kHz
TI0, TI1, TI2 input
tTIH, tTIL
VDD = 2.7 to 5.5 V
0.48
s
high-/low-level width
VDD = 1.8 to 5.5 V
1.8
s
Interrupt input high-/
tINTH, tINTL
INT0
IM02 = 0
Note 2
s
low-level width
IM02 = 1
10
s
INT1, 2, 4
10
s
KR0 to KR3
10
s
RESET low-level width
tRSL
10
s
Notes 1.
The cycle time (minimum instruction
execution time) of the CPU clock
(
Φ) is determined by the oscillation
frequency of the connected
resonator (and external clock), the
system clock control register (SCC)
and the processor clock control
register (PCC). The figure at the
right indicates the cycle time tCY
versus
supply
voltage
VDD
characteristic with the main system
clock operating.
2.
2tCY or 128/fx is set by setting the
interrupt mode register (IM0).
1
02
3
456
0.5
1
3
2
4
5
6
60
64
Supply voltage VDD [V]
tCY vs VDD
(At main system clock operation)
Cycle
time
t
CY
[
s]
Operation guaranteed
range
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