- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄200645 > UPD753108GK-XXX-9ET 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 PDF資料下載
參數(shù)資料
| 型號(hào)： | UPD753108GK-XXX-9ET |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 12 X 12 MM, PLASTIC, TQFP-64 |
| 文件頁(yè)數(shù)： | 38/100頁(yè) |
| 文件大?。?/td> | 736K |
| 代理商： | UPD753108GK-XXX-9ET |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)當(dāng)前第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)
40
PD753104, 753106, 753108
Data Sheet U10086EJ5V1DS
8. STANDBY FUNCTION
In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP
mode and HALT mode) are provided for the
PD753108.
Table 8-1. Operation Status in Standby Mode
Item
Mode
STOP Mode
HALT Mode
Set instruction
STOP instruction
HALT instruction
System clock when set
Settable only when the main system
Settable both by the main system clock
clock is used.
and subsystem clock.
Operation
Clock generator
Main system clock stops oscillation.
Only the CPU clock
Φ halts (oscillation
status
continues).
Basic interval timer/
Operation stops.
Operable only when the main system
watchdog timer
clock is oscillated.
BT mode : IRQBT is set in the
reference time interval
WT mode : Reset signal is generated
by BT overflow
Serial interface
Operable only when an external SCK
Operable only when an external SCK input
input is selected as the serial clock.
is selected as the serial clock or when the
main system clock is oscillated.
Timer/event counter
Operable only when a signal input to the
TI0 to TI2 pins is specified as the count
clock.
clock or when the main system clock is
oscillated.
Watch timer
Operable when fXT is selected as the
Operable.
count clock.
LCD controller/driver
Operable only when fXT is selected as the Operable.
LCDCL.
External interrupt
The INT1, 2, and 4 are operable.
Only the INT0 is not operatedNote.
CPU
The operation stops.
Release signal
Interrupt request signal sent from the operable hardware enabled by the interrupt
enable flag
Test request signal sent from the test source enabled by the test enable flag
RESET pin
Note
Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode
register (IM0).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD754304GS-XXX-A | 4-BIT, MROM, MICROCONTROLLER, PDSO36 |
| UPD75P116CW | 4-BIT, OTPROM, MICROCONTROLLER, PDIP64 |
| UPD780021AYCW-XXX | 8-BIT, MROM, 8.38 MHz, MICROCONTROLLER, PDIP64 |
| UPD780021AYGC-XXX-8BS | 8-BIT, MROM, 8.38 MHz, MICROCONTROLLER, PQFP64 |
| UPD780023AYCW(A)-XXX | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD753204013 | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD7554AG-597-E2 | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-597-E2-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-603-E2 | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7554AG-603-E2-A | 制造商:Renesas Electronics Corporation 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。