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參數(shù)資料
| 型號： | uPD72107L |
| 廠商： | NEC Corp. |
| 英文描述： | LAP-B CONTROLLER(Link Access Procedure Balanced mode) |
| 中文描述： | 鱲- B控制器（鏈路訪問過程平衡模式） |
| 文件頁數(shù)： | 8/32頁 |
| 文件大?。?/td> | 182K |
| 代理商： | UPD72107L |
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8
μ
PD72107
SDIP
QFP
QFJ
Active
Pin No.
Pin No.
Pin No.
Level
B/W
11
24
12
I
L/H
Specifies the data bus that accesses the external
(Byte/Word)
memory when bus master.
B/W = 0
Byte units (8 bits)
B/W = 1
Word units (16 bits)
After power-on, fix the status of the B/W pin.
In the case of word access, the lower data bus is the
contents data of even addresses.
READY
59
4
63
I
H
An input signal that is used to extend the MRD and
(Ready)
MWR signal widths output by the
μ
PD72107 to
adapt to low-speed memory. When the READY
signal is low level, the MRD and MWR signals
maintain active low. Do not change the READY
signal at any time other than the specified setup/
hold time.
HLDRQ
57
2
61
O
H
A hold request signal to the external host processor.
(Hold Request)
When a DMA operation is performed in the
μ
PD72107,
this signal is activated to switch from bus slave to
bus master.
HLDAK
58
3
62
I
H
A hold acknowledge signal from the external host
(Hold Acknowledge)
processor. When the
μ
PD72107 detects that this
signal is active, the bus slave switches to bus
master, and a DMA operation is started.
AEN
61
6
65
O
H
When bus master, this signal enables the latched
(Address Enable)
higher addresses and outputs them to system ad-
dress bus. This signal is also used for disabling
other system bus drivers.
A0, A1
15, 16
30, 31
17, 18
I/O
–
Bidirectional 3-state address lines.
3-state
When bus master (output)
Indicate the lower 2-bit addresses of memory access.
When bus slave (input)
Input addresses when the external host processor
I/O accesses the
μ
PD72107.
A2 to A15
17 to 30
32 to 47
19 to 32
O
–
When bus master
(except
3-state
Output bit 2 to bit 15 of memory access addresses.
40, 41)
When bus slave
Become high impedance.
I/O
Pin Name
Function
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