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參數(shù)資料
| 型號： | UPD72107 |
| 廠商： | NEC Corp. |
| 英文描述： | LAP-B CONTROLLER(Link Access Procedure Balanced mode) |
| 中文描述： | 鱲- B控制器（鏈路訪問過程平衡模式） |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 182K |
| 代理商： | UPD72107 |
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9
μ
PD72107
SDIP
QFP
QFJ
Active
Pin No.
Pin No.
Pin No.
Level
A16D8 to A23D15
31 to 38
48 to 58
33 to 41
I/O
–
Bidirectional 3-state address/data buses. Multiplex
(except 50,(except 35)
3-state
pins of the higher 16 bits to 23 bits of addresses
51, 55)
and the higher 8 bits to 15 bits of data.
D0 to D7
39 to 46
59 to 67
42 to 49
I/O
–
Bidirectional 3-state data buses.
(except 61)
3-state
When bus master
When writing to external memory, these pins become
input if reading at output.
When bus slave
Usually, these pins become high impedance. When
the external host processor reads I/O of the
μ
PD72107,
the internal register data is output.
CRQ
62
8
66
I
H
A signal requesting command execution to the
(Command
μ
PD72107 by the external host processor. The
Request)
μ
PD72107 starts fetching commands from on the
external memory at the rising edge of this signal.
INT
55
78
59
O
H
An interrupt signal from the
μ
PD72107 to the
(Interrupt)
external host processor.
CLRINT
56
79
60
I
H
A signal inactivating the INT signal being output by
(Clear Interrupt)
the
μ
PD72107. The
μ
PD72107 generates the CLRINT
signal in the LSI internal circuit at the rising edge of
this signal, and forcibly makes the INT output signal
low.
CTS
6
18
8
I
–
A general-purpose input pin.
(Clear To Send)
The
μ
PD72107 reports the “CTS pin change detection
status” to the external host processor when the
input level of this pin is changed in the general-
purpose input/output pin support (setting RSSL to
1 by the “system initialization command”). The
change of input level is recognized only when the
same level is sampled twice in succession after
sampling in 8-ms cycles and detecting the change.
Moreover, when the external host processor issues
a “general-purpose input/output pin read command”
to the
μ
PD72107, the
μ
PD72107 reports the pin
information of this pin to the external host processor
by a “general-purpose input/output pin read response
status”.
The change can be detected even in the clock input
stop status of TxC and RxC.
I/O
Pin Name
Function
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PDF描述 |
|---|---|
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