參數(shù)資料
型號(hào)： UPD70F3261YGF-JBT-A
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, PLASTIC, QFP-100
文件頁數(shù)： 125/129頁
文件大?。?/td> 8549K
代理商： UPD70F3261YGF-JBT-A
CHAPTER 3 CPU FUNCTION
User’s Manual U16541EJ5V1UD
95
(2/2)
Peripheral Function
Register Name
Access
k
C0GMABT,
C0GMABTD,
C0MASKaL, C0MASKaH,
C0LEC,
C0INFO,
C0ERC,
C0IE,
C0INTS,
C0BRP,
C0BTR,
C0TS
Read/write
(fXX/fCANMOD + 1)/(2 + j) (MIN.)
Note 3
(2
× fXX/fCANMOD + 1)/(2 + j) (MAX.)Note 3
C0GMCTRL,
C0GMCS,
C0CTRL
Read/write
(fXX/fCAN + 1)/(2 + j) (MIN.)
Note 3
(2×fXX/fCAN + 1)/(2 + j) (MAX.)
Note 3
Write
(fXX/fCANMOD + 1)/(2 + j) (MIN.)
Note 3
(2
× fXX/fCANMOD + 1)/(2 + j) (MAX.)Note 3
C0RGPT,
C0TGPT
Read
(3
× fXX/fCANMODE + 1)/(2 + j) (MIN.)Note 3
(4
× fXX/fCANMODE + 1)/(2 + j) (MAX.)Note 3
C0LIPT,
C0LOPT
Read
(3
× fXX/fCANMODE + 1)/(2 + j) (MIN.)Note
(4
× fXX/fCANMODE + 1)/(2 + j) (MAX.)Note 3
Write
(4×fXX/fCAN + 1)/(2 + j) (MIN.)
Note 3
(5×fXX/fCAN + 1)/(2 + j) (MAX.)
Note 3
C0MCTRLm
Read
(3×fXX/fCAN + 1)/(2 + j) (MIN.)
Note 3
(4×fXX/fCAN + 1)/(2 + j) (MAX.)
ote 3
Write (8 bits)
(4
× fXX/fCANMODE + 1)/(2 + j) (MIN.)Note 3
(5
× fXX/fCANMODE + 1)/(2 + j) (MAX.)Note 3
Write (16 bits)
(2
× fXX/fCANMODE + 1)/(2 + j) (MIN.)Note 3
(3
× fXX/fCANMODE + 1)/(2 + j) (MAX.)Note 3
CAN controller
Note 2
(m = 0 to 31, a = 1 to 4)
C0MDATA01m, C0MDATA0m,
C0MDATA1m, C0MDATA23m,
C0MDATA2m, C0MDATA3m,
C0MDATA45m, C0MDATA4m,
C0MDATA5m, C0MDATA67m,
C0MDATA6m, C0MDATA7m,
C0MDLCm,
C0MCONFm,
C0MIDLm, C0MIDHm
Read (8/16 bits)
(3
× fXX/fCANMODE + 1)/(2 + j) (MIN.)Note 3
(4
× fXX/fCANMODE + 1)/(2 + j) (MAX.)Note 3
CRC
CRCD
Write
1
Number of clocks necessary for access = 3 + i + j + (2 + j)
× k
Notes 1. I
2C bus versions (Y products) only
2. CAN controller versions only
3. Digits below the decimal point are rounded up.
Caution
Accessing the above registers is prohibited in the following statuses.
If a wait cycle is
generated, it can only be cleared by a reset.
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
<R>
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