
CHAPTER 11 FCAN CONTROLLER
539
User’s Manual U14492EJ5V0UD
11.8.7 Baud rate control function
(1) Prescaler
The FCAN controller of the V850E/IA1 includes a prescaler for dividing the clock supplied to the CAN (f
MEM1
).
This prescaler generates a clock (f
BTL
) that is based on a division ratio ranging from 2 to 128 applied to the
CAN base clock (f
MEM
) when the C1BRP register’s TLM bit = 0 and based on a division ratio ranging from 2 to
256 applied to the CAN base clock (f
MEM
) when the TLM bit = 1 (refer to
11.10 (26) CAN1 bit rate prescaler
register (C1BRP)
).
(2) Nominal bit time (8 to 25 time quantum)
A definition of 1 data bit time is shown below.
Remark
1 time quantum = 1/f
BTL
Figure 11-21. Nominal Bit Time
Nominal bit time
SJW
SJW
Phase segment 2
Phase segment 1
Sample point
Prop segment
Sync segment
Segment name
Segment length
Description
Sync segment
(Synchronization Segment)
1
This segment begins when resynchronization occurs.
Prop segment
(Propagation Segment)
1 to 8 (programmable)
This segment is used to absorb the delays caused by
the output buffer, CAN bus, and input buffer.
It is set to return an ACK signal until phase segment 1
begins.
Prop segment time
≥
(output buffer delay) + (CAN bus
delay) + (input buffer delay)
Phase segment 1
(Phase Buffer Segment 1)
1 to 8 (programmable)
Phase segment 2
(Phase Buffer Segment 2)
Maximum value from
phase segment 1 or
IPT
Note
(IPT = 0 to 2)
This segment is used to compensate for errors in the
data bit time. It accommodates a wide margin or error
but slows down communication speed.
SJW
(reSynchronization Jump Width)
1 to 4 (programmable)
This sets the range for bit synchronization.
Note
IPT: Information Processing Time
IPT is a period in which the current bit level is referenced and judgment for the next processing is
performed. IPT is indicated by the expression below using the clock supplied to CAN (f
MEM1
).
IPT = 1/f
MEM1
×
3