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CHAPTER 10 SERIAL INTERFACE FUNCTION
User’s Manual U14492EJ5V0UD
477
10.4 Clocked Serial Interfaces 0, 1 (CSI0, CSI1)
10.4.1 Features
High-speed transfer: Maximum 5 Mbps
Half-duplex communications
Master mode or slave mode can be selected
Transmission data length: 8 bits or 16 bits can be set
Transfer data direction can be switched between MSB first and LSB first
Eight clock signals can be selected (7 master clocks and 1 slave clock)
3-wire type SOn:
Serial transmit data output
SIn:
Serial receive data input
SCKn: Serial clock I/O
Interrupt sources: 1 type
Transmission/reception completion interrupt (INTCSIn)
Transmission/reception mode and reception-only mode can be specified
Two transmission buffers (SOTBFn/SOTBFLn, SOTBn/SOTBLn) and two reception buffers (SIRBn/SIRBLn,
SIRBEn/SIRBELn) are provided on chip
Single transfer mode and repeat transfer mode can be specified
Remark
n = 0, 1
10.4.2 Configuration
CSIn is controlled via the clocked serial interface mode register (CSIMn) (n = 0, 1). Transmission/reception of data
is performed by writing/reading the SIOn register (n = 0, 1).
(1) Clocked serial interface mode registers 0, 1 (CSIM0, CSIM1)
The CSIMn register is an 8-bit register that specifies the operation of CSIn.
(2) Clocked serial interface clock selection registers 0, 1 (CSIC0, CSIC1)
The CSICn register is an 8-bit register that controls the CSIn serial transfer operation.
(3) Serial I/O shift registers 0, 1 (SIO0, SIO1)
The SIOn register is a 16-bit shift register that converts parallel data into serial data.
The SIOn register is used for both transmission and reception.
Data is shifted in (reception) and shifted out (transmission) from the MSB or LSB side.
The actual transmission/reception operations are started up by accessing the buffer register.
(4) Serial I/O shift registers L0, L1 (SIOL0, SIOL1)
The SIOLn register is an 8-bit shift register that converts parallel data into serial data.
The SIOLn register is used for both transmission and reception.
Data is shifted in (reception) and shifted out (transmission) from the MSB or LSB side.
The actual transmission/reception operations are started up by accessing the buffer register.