參數(shù)資料
型號： UPD703032AYGF-XXX-3BA
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, PLASTIC, QFP-100
文件頁數(shù)： 33/54頁
文件大?。?/td> 507K
代理商： UPD703032AYGF-XXX-3BA
Data Sheet U14893EJ2V0DS
37
PD703032A, 703032AY, 70F3032A, 70F3032AY
(9) 3-wire variable length serial interface (CSI4) timing
(a) Master mode
(TA = –40 to +85
°°°°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
4.0 V
≤ EVDD ≤ 5.5 V
200
ns
SCK4 cycle
<68>
tKCY1
3.0 V
≤ EVDD < 4.0 V
400
ns
4.0 V
≤ EVDD ≤ 5.5 V
60
ns
SCK4 high-level width
<69>
tKH1
3.0 V
≤ EVDD < 4.0 V
140
ns
4.0 V
≤ EVDD ≤ 5.5 V
60
ns
SCK4 low-level width
<70>
tKL1
3.0 V
≤ EVDD < 4.0 V
140
ns
4.0 V
≤ EVDD ≤ 5.5 V
25
ns
SI4 setup time (to SCK4
↑)
<71>
tSIK1
3.0 V
≤ EVDD < 4.0 V
50
ns
SI4 hold time (from SCK4
↑)
<72>
tKSI1
20
ns
Delay time from SCK4
↓ to SO4
output
<73>
tKSO1
55
ns
(b) Slave mode
(TA = –40 to +85
°°°°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
4.0 V
≤ EVDD ≤ 5.5 V
200
ns
SCK4 cycle
<68>
tKCY2
3.0 V
≤ EVDD < 4.0 V
400
ns
4.0 V
≤ EVDD ≤ 5.5 V
60
ns
SCK4 high-level width
<69>
tKH2
3.0 V
≤ EVDD < 4.0 V
140
ns
4.0 V
≤ EVDD ≤ 5.5 V
60
ns
SCK4 low-level width
<70>
tKL2
3.0 V
≤ EVDD < 4.0 V
140
ns
4.0 V
≤ EVDD ≤ 5.5 V
25
ns
SI4 setup time (to SCK4
↑)
<71>
tSIK2
3.0 V
≤ EVDD < 4.0 V
50
ns
SI4 hold time (from SCK4
↑)
<72>
tKSI2
20
ns
4.0 V
≤ EVDD ≤ 5.5 V
55
ns
Delay time from SCK4
↓ to SO4
output
<73>
tKSO2
3.0 V
≤ EVDD < 4.0 V
100
ns
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