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參數(shù)資料
| 型號： | UPD4702 |
| 廠商： | NEC Corp. |
| 元件分類： | 通用總線功能 |
| 英文描述： | INCREMENTAL ENCODER 8-BIT UP/DOWN COUNTER CMOS INTEGRATED CIRCUITS |
| 中文描述： | 增量式編碼器8位加/減計數(shù)器CMOS集成電路 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 167K |
| 代理商： | UPD4702 |
3
μ
PD4702
1.
DESCRIPTION OF OPERATIONS
(1)
Count operation
The
μ
PD4702 incorporates a phase discrimination circuit, and counts by 4-multiplication of the A and B input 2-
phase pulses. Therefore, a count operation is performed by an A input edge and a B input edge.
Fig. 1 Count Operation Timing Chart
Forward (Up-Count)
Reverse (Down-Count)
A Input
Count Operation
B Input
2
4
3
1
1
3
5
4
2
0
(2)
Latch operation
An R-S flip-flop is inserted in the strobe input of the latch circuit as shown in Fig. 2, and when STB changes from
“H” to “L” during a count operation, the internal latch signal STB remains at “H” until the end of the count operation.
Therefore, the count value is latched correctly even if STB input is performed asynchronously from the A and B input
(if STB changes from “H” to “L” within t
SABSTB
(40 ns) after the A input or B input edge, the latch contents will be
either the pre-count or post-count value). However, when a
μ
PD4704 is added, the correct value cannot be latched
if all digits are latched simultaneously when a carry or borrow is generated (the high-order digit may be latched
before carry/borrow transmission).
Fig. 2 STB Input Circuit
From Phase Discrimination Circuit
(Count Pulse)
STB
STB
Latched
when L
A, B Inputs
STB
t
SABSTB
If t
SABSTB
is 40 ns or longer, the post-count value
is input to the latch.
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| UPD4702C-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
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