參數(shù)資料
型號(hào)： UPD44325084F5-E50-EQ2-A
元件分類： SRAM
英文描述： 4M X 8 QDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
文件頁(yè)數(shù)： 4/40頁(yè)
文件大?。?/td> 387K
代理商： UPD44325084F5-E50-EQ2-A
12
Data Sheet
M16784EJ4V0DS
μPD44325084, 44325094, 44325184, 44325364
Power-on Sequence
The following timing charts show the recommended power-on sequence, i.e., when starting the clock after VDD/VDDQ
stable and when starting the clock before VDD/VDDQ stable.
1. Clock starts after VDD/VDDQ stable
The clock is supplied from a controller.
(a)
VDD/VDDQ
VDD/VDDQ Stable (<
±0.1 V DC per 50 ns)
DLL#
Clock Start
Normal Operation
Start
Clock
Fix HIGH (or tied to VDDQ)
20 ns (MIN.)
1,024 cycles or more
Stable Clock
Note
Note Input a stable clock from the start.
(b)
VDD/VDDQ
DLL#
Switched to HIGH after Clock is stable.
Unstable Clock
(level, frequency)
VDD/VDDQ Stable (<
±0.1 V DC per 50 ns)
Clock
Clock Start
Normal Operation
Start
1,024 cycles or more
Stable Clock
(c)
VDD/VDDQ
DLL#
30 ns. (MIN.)
Clock Stop
VDD/VDDQ Stable (<
±0.1 V DC per 50 ns)
Fix HIGH (or tied to VDDQ)
Unstable Clock
(level, frequency)
Clock
Clock Start
Normal Operation
Start
1,024 cycles or more
Stable Clock
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD44325092BF5-E40-FQ1-A 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 4M x 9-Bit 0.45ns 165-Pin BGA
UPD44325094BF5-E40-FQ1 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA
UPD44325094BF5-E40-FQ1-A 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA
UPD44325182BF5-E33-FQ1-A 制造商:Renesas Electronics Corporation 功能描述:
UPD44325182BF5-E40-FQ1 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays
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