參數(shù)資料
型號(hào)： UPD44325084F5-E50-EQ2-A
元件分類(lèi)： SRAM
英文描述： 4M X 8 QDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
文件頁(yè)數(shù)： 16/40頁(yè)
文件大?。?/td> 387K
代理商： UPD44325084F5-E50-EQ2-A
23
Data Sheet
M16784EJ4V0DS
μPD44325084, 44325094, 44325184, 44325364
Read and Write Timing
K
Address
Data in
K#
24
6
13
5
7
TKHK#H TK#HKH
C
C#
TKHCH
NOP
READ
TKHKL
TKLKH
Q00
Q02
Data out
Q01
Q03
R#
W#
TKHKL
TKLKH
TCHQX1
TCHQX
TCHQZ
D10
D12
D11
D13
TDVKH TKHDX
TDVKH
TKHDX
TKHKH
TIVKH
TKHIX
TAVKH
TKHAX
CQ
CQ#
TCHQV
TCHCQX
TCHCQV
TCHCQX
TCHCQV
WRITE
NOP
Qx3
TCHQX
TCHQV
WRITE
TIVKH
TKHIX
A0
A1
A2
A3
D30
D32
D31
D33
Q20
Q22
Q21
Q23
Qx2
TKHK#H TK#HKH
TKHCH
TKHKH
TCQHQV
TCQHQX
Remarks 1. Q00 refers to output from address A0+0.
Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.
2. Outputs are disabled (high impedance) 3.5 clocks after the last READ (R# = LOW) is input in the
sequences of [READ]-[NOP]-[NOP], [READ]-[WRITE]-[NOP] and [READ]-[NOP]-[WRITE].
3. In this example, if address A2 = A1, data Q20 = D10, Q21 = D11, Q22 = D12 and Q23 = D13.
Write data is forwarded immediately as read results.
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參數(shù)描述
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