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參數(shù)資料
| 型號(hào)： | UPD44324362F5-E37-EQ2-A |
| 廠商： | NEC Corp. |
| 元件分類： | DRAM |
| 英文描述： | 36M-BIT DDRII SRAM 2-WORD BURST OPERATION |
| 中文描述： | 36M條位SRAM的2條DDRII字爆發(fā)運(yùn)作 |
| 文件頁(yè)數(shù)： | 28/40頁(yè) |
| 文件大小： | 361K |
| 代理商： | UPD44324362F5-E37-EQ2-A |
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28
Data Sheet M16780EJ3V0DS
μ
PD44324082, 44324092, 44324182, 44324362
Output Pin States of CQ, CQ# and Q
Instructions
Control-Register Status
Output Pin Status
Note
CQ,CQ#
Q
EXTEST
0
Update
Hi-Z
1
Update
Update
IDCODE
0
SRAM
SRAM
1
SRAM
SRAM
SAMPLE-Z
0
Hi-Z
Hi-Z
1
Hi-Z
Hi-Z
SAMPLE
0
SRAM
SRAM
1
SRAM
SRAM
BYPASS
0
SRAM
SRAM
1
SRAM
SRAM
Remark
The output pin statuses during each instruction vary according
to the Control-Register status (value of Boundary Scan
Register, bit no. 109).
There are three statuses:
Update : Contents of the “Update Register” are output to
the output pin (QDR Pad).
SRAM : Contents of the SRAM internal output “SRAM
Output” are output to the output pin (QDR Pad).
Hi-Z : The output pin (QDR Pad) becomes Hi-Z by
controlling of the “Hi-Z JTAG ctrl”.
The Control-Register status is set during Update-DR at the
EXTEST or SAMPLE instruction.
SRAM
CAPTURE
Register
Boundary Scan
Register
Update
Register
QDR
Pad
SRAM
Output
Driver
Hi-Z
JTAG ctrl
Hi-Z
Update
SRAM
Output
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| UPD44324362F5-E50-EQ2-A | 36M-BIT DDRII SRAM 2-WORD BURST OPERATION |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44324365BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324365BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44325084BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA |
| UPD44325092BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 4M x 9-Bit 0.45ns 165-Pin BGA |
| UPD44325094BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA |
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