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參數(shù)資料
| 型號： | UPD44324184F5-E50-EQ2 |
| 廠商： | NEC Corp. |
| 英文描述： | 36M-BIT DDRII SRAM 4-WORD BURST OPERAT |
| 中文描述： | 36M條位SRAM的4條DDRII詞爆生產(chǎn)營運 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 315K |
| 代理商： | UPD44324184F5-E50-EQ2 |
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17
Preliminary Data Sheet
M16781EJ1V0DS
μ
PD44324084, 44324094, 44324184, 44324364
Notes 1.
The device will operate at clock frequencies slower than TKHKH(MAX.).
2.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
3.
V
DD
slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention.
DLL lock time begins once V
DD
and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
4.
Echo clock is very tightly controlled to data valid / data hold. By design, there is a
±
0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
5.
This is a synchronous device. All addresses, data and control lines must meet the specified setup
and hold times for all latching clock edges.
Remarks 1.
This parameter is sampled.
2.
Test conditions as specified with the output loading as shown in AC Test Conditions
unless otherwise noted.
3.
Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4.
If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters.
5.
V
DD
Q is 1.5 V DC.
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| UPD44324185BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
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| UPD44324362BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
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