參數(shù)資料
型號(hào)： UPD44165184F5-E50-EQ1
廠商： NEC Corp.
英文描述： 18M-BIT QDRII SRAM 4-WORD BURST OPERATION
中文描述： 1800萬(wàn)位推出QDRII SRAM的4個(gè)字爆發(fā)運(yùn)作
文件頁(yè)數(shù)： 22/32頁(yè)
文件大小： 392K
代理商： UPD44165184F5-E50-EQ1
22
Data Sheet M15825EJ7V
1
DS
μ
PD44165084, 44165184, 44165364
JTAG Instructions
Instructions
Description
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-
scan register cells at output pins are used to apply test vectors, while those at input pins capture test
results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,
the output driver is turned on and the PRELOAD data is driven onto the output pins.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed
in the test-logic-reset state.
BYPASS
The BYPASS instruction is loaded in the instruction register when the bypass register is placed between
TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the
board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE / PRELOAD
SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /
PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-DR
state loads the data in the RAMs input and Q pins into the boundary scan register. Because the RAM
clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the
I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing
the TAP to sample metastable input will not harm the device, repeatable results cannot be expected.
RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus
hold time (t
CS
plus t
CH
). The RAMs clock inputs need not be paused for any other TAP operation except
capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state
then places the boundary scan register between the TDI and TDO pins.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced to an inactive
drive state (high impedance) and the boundary register is connected between TDI and TDO when the
TAP controller is moved to the shift-DR state.
JTAG Instruction Coding
IR2
IR1
IR0
Instruction
Note
0
0
0
EXTEST
0
0
1
IDCODE
0
1
0
SAMPLE-Z
1
0
1
1
RESERVED
1
0
0
SAMPLE / PRELOAD
1
0
1
RESERVED
1
1
0
RESERVED
1
1
1
BYPASS
Note 1.
TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.
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