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參數(shù)資料
| 型號(hào)： | UPD4416001 |
| 廠商： | NEC Corp. |
| 英文描述： | 16M-BIT CMOS FAST SRAM 16M-WORD BY 1-BIT |
| 中文描述： | 1,600位CMOS快速靜態(tài)存儲(chǔ)器1,600 - Word的1位 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大小： | 83K |
| 代理商： | UPD4416001 |
Data Sheet M14077EJ3V0DS
7
μ
PD4416001
Write Cycle
Parameter
Symbol
-A15
-A17
Unit
Notes
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
15
17
ns
/CS to end of write
t
CW
10
11
ns
Address valid to end of write
t
AW
10
11
ns
Write pulse width
t
WP
10
11
ns
Data valid to end of write
t
DW
7
8
ns
Data hold time
t
DH
0
0
ns
Address setup time
t
AS
0
0
ns
Write recovery time
t
WR
1
1
ns
/WE to output in high impedance
t
WHZ
7
8
ns
1, 2
Output active from end of write
t
OW
3
3
ns
Notes
1.
Transition is measured at
±
200 mV from steady-state voltage with the output load shown in
Figure 2
.
2.
These parameters are periodically sampled and not 100% tested.
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW
t
WP
t
AS
t
WR
t
DW
t
DH
Data in
Address (Input)
/CS (Input)
/WE (Input)
D
IN
(Input)
D
OUT
(Output)
t
ACS
t
CLZ
t
OH
t
AA
t
OW
t
WHZ
t
AW
High impedance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1.
Write operation is done during the overlap time of a low level /CS, a low level /WE.
2.
During t
WHZ
, D
OUT
pins are in the output state, therefore the input signals of opposite phase to the
output must not be applied.
3.
When /WE is at low level, the D
OUT
pins are always high impedance. When /WE is at high level, read
operation is executed. Therefore /OE should be at high level to make the D
OUT
pins high impedance.
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