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參數(shù)資料
| 型號： | UPD2845GR-E1 |
| 廠商： | NEC Corp. |
| 英文描述： | 1 V, 1.3 mA, 94MHz PLL SYNTHESIZER LSI FOR PAGER SYSTEM |
| 中文描述： | 1伏，1.3毫安，94MHz PLL頻率合成器大規(guī)模集成電路的尋呼系統(tǒng) |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 144K |
| 代理商： | UPD2845GR-E1 |
11
P
PD2845GR
NT = 32M + S
= 32
u
{(D1
u
2
(D10
u
2
2
12
) + (D2
u
2
11
) + (D3
u
2
10
) + (D4
u
2
9
) + (D5
u
2
8
) + (D6
u
2
7
) + (D7
u
2
6
) + (D8
u
2
5
) + (D9
u
2
4
) +
3
) + (D11
u
2
2
) + (D12
u
2
1
) + (D13
u
2
0
)} + {(D14
u
2
4
) + (D15
u
2
3
) + (D16
u
2
2
) + (D17
u
2
1
) + (D18
u
0
)}
NT = (D1
u
2
(D10
u
2
17
) + (D2
u
2
16
) + (D3
u
2
15
) + (D4
u
2
14
) + (D5
u
2
13
) + (D6
u
2
12
) + (D7
u
2
11
) + (D8
u
2
10
) + (D9
u
2
9
) +
8
) + (D11
u
2
7
) + (D12
u
2
6
) + (D13
u
2
5
) + (D14
u
2
4
) + (D15
u
2
3
) + (D16
u
2
2
) + (D17
u
2
1
) + (D18
u
2
0
)
Thus, total divide ratio of input signal divider ‘NT’ can be transferred to binary-code in order to setting data ‘D1 to
D18’ input. (D1 should be top digit and D18 should be bottom digit.)
Charge pump output selection data
D22
D21
EO Pin
(To use internal
charge pump)
EOP, EO Pin
(To use external
charge pump)
0
0
Hi- Impedance
OFF
0
1
Hi-Impedance
OUTPUT
1
0
OUTPUT
OFF
1
1
OUTPUT
OUTPUT
“0” = Low, “1” = High
(3) Setting for reference counter
D22
A
D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
A
A = 0
no assigned
reference counter : R
(13 bits 2 to 8 191)
TEST BIT
(FR pin)
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
2
10
2
11
2
12
0
1
CAUTION D1 to D7 are not assigned for setting but CLK signals must be input because of the bit
construction.
RT = 2
u
R
RT = 2
u
{(D10
u
2
(D18
u
2
12
) + (D11
u
2
11
) + (D12
u
2
10
) + (D13
u
2
9
) + (D14
u
2
8
) + (D15
u
2
7
) + (D16
u
2
6
) + (D17
u
2
5
) +
4
) + (D19
u
2
3
) + (D20
u
2
2
) + (D21
u
2
1
) + (D22
u
2
0
)}
*TEST BIT:
for IC tester (FR pin) use or not use (PLL operation).
for normally PLL operation, input D9 = 0, D8 = 1 (FR pin = output L).
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