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參數(shù)資料
| 型號： | UPD2845GR-E1 |
| 廠商： | NEC Corp. |
| 英文描述： | 1 V, 1.3 mA, 94MHz PLL SYNTHESIZER LSI FOR PAGER SYSTEM |
| 中文描述： | 1伏，1.3毫安，94MHz PLL頻率合成器大規(guī)模集成電路的尋呼系統(tǒng) |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 144K |
| 代理商： | UPD2845GR-E1 |
10
P
PD2845GR
Data format of shift register
Foundaly constraction of shift register
A D22D21D20D19D18D17D16D15D14D13D12D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
first bit
MSB
last bit
LSB
LE
DATA
CLK
(1) Setting for data selection bit
Data selection bit: last A bit can govern the latch selection.
Data selection bit’s construction and function
A
Function
1
Setting for swallow and main counter’s divide ratio.
Setting for charge pump output selection.
0
Setting for reference counter’s divide ratio.
“0” = Low, “1” = High
(2) Setting for swallow/main counter’s data and charge pump output selection
Bit constraction of setting for swallow/main counter and charge pump output selection
D22
A
D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
A
A = 1
charge
pump
output
selection
no
assigned
swallow counter : S
(5 bits 0 to 31)
main counter : M
(13 bits 32 to 8 191)
2
0
2
1
2
2
2
3
2
4
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
2
10
2
11
2
12
CAUTION D19, D20 are not assigned for setting but CLK signals must be input because of the bit
construction.
SWALLOW COUNTER DATA
S = (D14
u
2
4
) + (D15
u
2
3
) + (D16
u
2
2
) + (D17
u
2
1
) + (D18
u
2
0
)
MAIN COUNTER DATA
M = (D1
u
2
(D10
u
2
12
) + (D2
u
2
11
) + (D3
u
2
10
) + (D4
u
2
9
) + (D5
u
2
8
) + (D6
u
2
7
) + (D7
u
2
6
) + (D8
u
2
5
) + (D9
u
2
4
) +
3
) + (D11
u
2
2
) + (D12
u
2
1
) + (D13
u
2
0
)
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|---|---|
| UPD2845GR-E2 | 制造商:NEC 制造商全稱:NEC 功能描述:1 V, 1.3 mA, 94MHz PLL SYNTHESIZER LSI FOR PAGER SYSTEM |
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